Patents by Inventor Ngek Leong Guok

Ngek Leong Guok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9367500
    Abstract: In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined backbone including: receiving a plurality of unarbitrated grant requests at an agent bus interface from a plurality of masters, each requesting access to a backbone connected via a common request channel; determining which of the unarbitrated grant requests is to issue first as a final grant request; storing a master identifier code for the final grant request into a FIFO buffer, the master identifier code associating the final grant request with the issuing master among the plurality of masters; waiting for a backbone grant; and presenting the master identifier code for the final grant request to an agent bus interface, wherein the agent bus interface communicates a command and data for processing via a backbone responsive to the backbone grant to fulfill the final grant request.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Ngek Leong Guok, Kah Meng Yeem, Poh Thiam Teoh, Jennifer Chin, Su Wei Lim
  • Patent number: 9268568
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for enabling an agent interfacing with a pipelined backbone to locally handle transactions while obeying an ordering rule including, for example, receiving a transaction which requests access to a backbone; decoding routing destination information from the transaction received, in which the decoded routing destination information designates the transaction to be processed either locally or processed via the backbone; storing the decoded routing destination information and the transaction into a First-In-First-Out (FIFO) buffer; retrieving the decoded routing destination information and the transaction from the FIFO buffer; and processing the transaction locally or via the backbone based on the decoded routing destination information retrieved from the FIFO buffer with the transaction.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Ngek Leong Guok, Kah Meng Yeem, Poh Thiam Teoh, Su Wei Lim
  • Publication number: 20140207986
    Abstract: In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined backbone including: receiving a plurality of unarbitrated grant requests at an agent bus interface from a plurality of masters, each requesting access to a backbone connected via a common request channel; determining which of the unarbitrated grant requests is to issue first as a final grant request; storing a master identifier code for the final grant request into a FIFO buffer, the master identifier code associating the final grant request with the issuing master among the plurality of masters; waiting for a backbone grant; and presenting the master identifier code for the final grant request to an agent bus interface, wherein the agent bus interface communicates a command and data for processing via a backbone responsive to the backbone grant to fulfill the final grant request.
    Type: Application
    Filed: November 9, 2011
    Publication date: July 24, 2014
    Inventors: Ngek Leong Guok, Kah Meng Yeem, Poh Thiam Teoh, Jennifer Chin, Su Wei Lim
  • Patent number: 8745296
    Abstract: An embodiment may include circuitry to (a) convert, at least in part, at least one serial storage protocol compatible frame into at least one packet that is compatible, at least in part, with a multi-lane input/output (I/O) protocol, and/or (b) convert, at least in part, the at least one packet into the at least one frame. The at least one packet may be transmitted via a physical layer that is compatible, at least in part, with the multi-lane I/O protocol. The at least one packet may comprise frame information structure (FIS) information of the at least one frame.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Ngek Leong Guok, Chai Huat Gan, Eng Hun Ooi
  • Publication number: 20140095742
    Abstract: An embodiment may include circuitry to (a) convert, at least in part, at least one serial storage protocol compatible frame into at least one packet that is compatible, at least in part, with a multi-lane input/output (I/O) protocol, and/or (b) convert, at least in part, the at least one packet into the at least one frame. The at least one packet may be transmitted via a physical layer that is compatible, at least in part, with the multi-lane I/O protocol. The at least one packet may comprise frame information structure (FIS) information of the at least one frame.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 3, 2014
    Inventors: Ngek Leong Guok, Chai Huat Gan, Eng Hun Ooi
  • Publication number: 20130283013
    Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for enabling an agent interfacing with a pipelined backbone to locally handle transactions while obeying an ordering rule including, for example, receiving a transaction which requests access to a backbone; decoding routing destination information from the transaction received, in which the decoded routing destination information designates the transaction to be processed either locally or processed via the backbone; storing the decoded routing destination information and the transaction into a First-In-First-Out (FIFO) buffer; retrieving the decoded routing destination information and the transaction from the FIFO buffer; and processing the transaction locally or via the backbone based on the decoded routing destination information retrieved from the FIFO buffer with the transaction.
    Type: Application
    Filed: November 9, 2011
    Publication date: October 24, 2013
    Inventors: Ngek Leong Guok, Kah Meng Yeem, Poh Thiam Teoh, Su Wei Lim
  • Patent number: 7844777
    Abstract: In one embodiment, the present invention includes a host controller having a cache memory to store entries each including, at least, a command header (CH) portion having data associated with a command from the host controller to one of multiple devices coupled to a port multiplier, and a physical region descriptor (PRD) portion to store address information associated with a next address for data transfer with regard to the command. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Ngek Leong Guok, Eng Hun Ooi
  • Publication number: 20090006670
    Abstract: In one embodiment, the present invention includes a host controller having a cache memory to store entries each including, at least, a command header (CH) portion having data associated with a command from the host controller to one of multiple devices coupled to a port multiplier, and a physical region descriptor (PRD) portion to store address information associated with a next address for data transfer with regard to the command. Other embodiments are described and claimed.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Ngek Leong Guok, Eng Hun Ooi