Abstract: An apparatus for incorporating a metallic foil into a semiconductor package includes a carrier embossed with a multiplicity of cavities. Each of the cavities define a pedestal recessed with the cavities which penetrate only partially through the thickness of the carrier. A metallic foil overlying a pattern with the pedestals in direct contact and help support the metallic foil with the metallic foil pressed into at least some of the cavities. In other embodiments, a gap is between the metallic foil and bottoms of the cavities in a substrate. Integrated circuit dice are attached to the foil. Each die is attached to the foil in a region of the foil overlying a portion of the at least one device area pattern. Bonding wires electrically connect the integrated circuit dice to the foil.

Abstract: The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages.

Abstract: Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution.

Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

Abstract: A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 ?m to about 35 ?m.

Abstract: The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

Abstract: Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution.

Abstract: The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

Abstract: A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 ?m to about 35 ?m.

Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: Techniques for forming micro-array style packages are disclosed. A matrix of isolated contact posts are placed on an adhesive carrier. Dice are then mounted (directly or indirectly) on the carrier and each die is electrically connected to a plurality of associated contacts. The dice and portions of the contacts are then encapsulated in a manner that leaves at least bottom portions of the contacts exposed to facilitate electrical connection to external devices. The encapsulant serves to hold the contacts in place after the carrier has been removed.

Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

Abstract: Methods for minimizing warpage of a welded foil carrier structure used in the packaging of integrated circuits are described. Portions of a metallic foil are ultrasonically welded to a carrier to form a foil carrier structure. The ultrasonic welding helps define a panel in the metallic foil that is suitable for packaging integrated circuits. Warpage of the thin foil can be limited in various ways. By way of example, an intermittent welding pattern that extends along the edges of the panel may be formed. Slots may be cut to define sections in the foil carrier structure. Materials for the metallic foil and the carrier may be selected to have similar coefficients of thermal expansion. An appropriate thickness for the metallic foil and the carrier may be selected, such that the warpage of the welded foil carrier structure is limited when the foil carrier structure is subjected to large increases in temperature. Foil carrier structures for use in the above methods are also described.

Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.

Abstract: A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.