Abstract: A design structure including a semiconductor storage array having a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.

Abstract: A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.

Abstract: A method and a reference circuit for bias current switching are provided for implementing an integrated temperature sensor. A first bias current is generated and constantly applied to a thermal sensing diode. A second bias current is provided to the thermal sensing diode by selectively switching a multiplied current from a current multiplier to the thermal sensing diode or to a load diode. The reference circuit includes a reference current source coupled to current mirror. The current mirror provides a first bias current to a thermal sensing diode. The current mirror is coupled to a current multiplier that provides a multiplied current. A second bias current to the thermal sensing diode includes the first bias current and the multiplied current from the current multiplier. The second bias current to the thermal sensing diode is provided by selectively switching the multiplied current between the thermal sensing diode and a dummy load diode.

Abstract: Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.

Abstract: Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is produced by the failure memory. The disable signal is a required input to a user logic function, such as an off chip driver, an off chip receiver, a clock, or a static random access memory. When the radiation detector detects radiation, that detection is stored in the failure memory. The disable signal, when active, causes some or all of the user function to be inoperative. This invention is particularly important when the semiconductor chip is produced in a silicon on insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process, which is naturally radiation resistant.

Abstract: Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is produced by the failure memory. The disable signal is a required input to a user logic function, such as an off chip driver, an off chip receiver, a clock, or a static random access memory. When the radiation detector detects radiation, that detection is stored in the failure memory. The disable signal, when active, causes some or all of the user function to be inoperative. This invention is particularly important when the semiconductor chip is produced in a silicon on insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process, which is naturally radiation resistant.

Abstract: A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.

Abstract: A method and apparatus for reducing parasitic bipolar transistor leakage current in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS). A capacitor is operatively coupled between the base and emitter terminals of the parasitic bipolar transistor. The capacitor effectively reduces the base to emitter voltage of the parasitic transistor thereby reducing leakage current generated at the collector terminal.

Abstract: Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiments. The apparatus may comprise: a first level of logic for receiving at least two binary numbers and generating multi-bit P, G, Z, and K carry signals; a second level of logic receiving the multi-bit P, G, Z, and K carry signals and generating multi-bit section-based carry signals; and a third level of logic receiving the multi-bit section-based carry signals and generating a sum of the received binary numbers, the third level of logic comprising: a plurality of domino logic gates forming sum bits using the multi-bit section-based P, G, Z, and K carry signals.

Abstract: Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit.

Abstract: A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.

Abstract: Measurement methods and a ring oscillator circuit are provided for evaluating dynamic circuits. The ring oscillator circuit includes a one-shot pulse generator receiving a single transition input signal and producing a pulse output signal having a rising transition and falling transition. The dynamic circuit to be evaluated is coupled to an output of the one-shot pulse generator receiving the pulse output signal of the one-shot pulse generator and producing a delayed output pulse at an output. A divide-by-two circuit is coupled to the output of the dynamic circuit to be evaluated. An output signal of the divide-by-two circuit is fed back to the one-shot pulse generator, and the cycle is repeated, thus oscillating. A multiplexer is connected between output of the dynamic circuit to be evaluated and the divide-by-two circuit.

Abstract: A fully dynamic logic network and method of operation thereof. The dynamic logic network includes a number of dynamic switching circuits, where each of dynamic switching circuits generates an output signal. In an advantageous embodiment, each of the dynamic switching circuits is a dynamic domino gate. The dynamic logic network also includes a dynamic logic circuit that is coupled to the dynamic switching circuits. The dynamic logic circuit, in turn, includes a clock generation circuit and a logic switching circuit that in a preferred embodiment is a dynamic NOR, or alternatively, NAND gate. The clock generation circuit receives the output signals from the dynamic switching circuits and generates, in response thereto, a control signal. The logic switching circuit also receives the output signals from the dynamic switching circuits and generates a logic output signal in response to a state of the control signal generated by the clock generation circuit.

Abstract: An electronic circuit and a method of designing the electronic circuit having conductive fill stripes which are electrically attached to the power distribution or to the signal routing of the circuit. Preferably, the conductive fill stripes are electrically attached to the power distribution and are interspersed between the power buses and signal wires on the various metal layers to satisfy the metal density requirements of integrated circuit and chip manufacturing. The conductive fill stripes are added during the design process after the placement of the power distribution and signal routing so that electrical continuity between the conductive fill stripes and the connecting bus, metal density requirements, other design rules and logic verification can be completed as the rest of the chip is designed.

Abstract: A parallel static adder for adding two n-bit operands, the adder including half-sum circuitry, summing circuitry, and carry look-ahead circuitry. The half-sum circuitry receives a pair of same-order bits from the two n-bit operands, and generates a plurality of half-sum signals for each of the pairs of same-order bits. The summing circuit adds a corresponding half-sum signal to a carry signal from a preceding lower order summing circuit. The carry look-ahead circuit generates a carry signal for higher order summing circuits. Each of the carry look-ahead circuits includes a plurality of logic arrays, each comprising one or more field effect devices coupled in parallel between a first node and a second node, where each of the field effect devices has a gate input to receive lower order addend and augend bits in accordance with a predetermined carry look-ahead equation.

Abstract: A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.

Abstract: The present invention involves a BICMOS logic switching circuit biased between upper and lower supply voltages. This circuit includes a CMOS logic circuit driven by a plurality of logic input signals. This logic switching circuit also has a driving circuit coupled to the CMOS logic switching circuit and includes an output node, a first bipolar transistor, and a second bipolar transistor. The first bipolar transistor is coupled in series with the second bipolar transistor with the output node therebetween for providing an output signal on the output node, wherein the second bipolar transistor has a base directly coupled to a field effect transistor switch coupled to the upper supply voltage. The field effect transistor switch is controlled by logic input signals.

Abstract: An ECL logic circuit uses a single resistor in place of separate current-source and emitter-follower resistors. A single tap connects a point on this resistor to the ground bus, and the signal-output line connects to this resistor by a contact which is separate from the contact connecting the emitter of the ouput transistor to the resistor.