Abstract: A method and system for channelizing a Passive Optical Network (PON) Media Access Controller (MAC) includes increasing a clock rate of each of one or more PON MAC(s) to create communication lanes each comprising a plurality of N channels. The PONs are channelized according to NX, where N equals a number of ports supported by the MAC and X equals a designated operating PON MAC clocking rate allowing for leveraging of existing Passive Optical Network (PON) infrastructures to provide a more power efficient and physically smaller MAC layer for OLTs.

Abstract: A method and system for channelizing a Passive Optical Network (PON) Media Access Controller (MAC) includes increasing a clock rate of each of one or more PON MAC(s) to create communication lanes each comprising a plurality of N channels. The PONs are channelized according to NX, where N equals a number of ports supported by the MAC and X equals a designated operating PON MAC clocking rate allowing for leveraging of existing Passive Optical Network (PON) infrastructures to provide a more power efficient and physically smaller MAC layer for OLTs.

Abstract: One embodiment of the present invention provides a system that decrypts downstream data in an Ethernet passive optical network (EPON). During operation, the system receives a data frame which is encrypted based on a remote input block and a session key, wherein the remote input block is constructed based on a remote cipher counter and a remote block counter. The system adjusts a local cipher counter based on a received checksum located in a preamble of the data frame, wherein the local cipher counter is substantially synchronized with the remote cipher counter. In addition, the system truncates the local cipher counter by discarding n least significant bits thereof. The system then constructs a local input block based on the truncated cipher counter and a local block counter for the received data frame. Next, the system decrypts the data frame based on the local input block and the session key.

Abstract: An asynchronous switching circuit for multiple indeterminate bursting clocks. In one embodiment, the present invention recites a clock-switching circuit that provides a single unclipped and glitch-free clock signal at its output from among multiple clock inputs. The clock-switching circuit is comprised of a plurality of asynchronously-enabled clock circuits, a plurality of blocking circuits, a synchronizing clock, and a logic gate. Each of the plurality of blocking circuits has an input lead respectively coupled to one of the plurality of asynchronously-enabled clock circuits, each of the plurality of blocking circuits also has an output coupled to all of the plurality of asynchronously-enabled clock circuits except the one to which its input is coupled. The synchronizing clock is coupled to each of the plurality of blocking circuits while the logic gate is coupled to each of the plurality of asynchronously-enabled clock circuits.