Abstract: One embodiment provides a system for decrypting data frames in an Ethernet passive optical network (EPON). During operation, the system maintains a local cipher counter at a local node, and receives from a remote node a data frame which is encrypted based on a remote input block and a session key. The remote input block is constructed based on the remote cipher counter and a remote block counter. The system updates the local cipher counter based on a received field located in a preamble of the data frame, truncates the local cipher counter by discarding a number of least significant bits, and constructs for the received data frame a local input block based on the truncated local cipher counter, the received field, and a local block counter. The system then decrypts the data frame based on the local input block and the session key.

Abstract: One embodiment provides a system for decrypting data frames in an Ethernet passive optical network (EPON). During operation, the system maintains a local cipher counter at a local node, and receives from a remote node a data frame which is encrypted based on a remote input block and a session key. The remote input block is constructed based on the remote cipher counter and a remote block counter. The system updates the local cipher counter based on a received field located in a preamble of the data frame, truncates the local cipher counter by discarding a number of least significant bits, and constructs for the received data frame a local input block based on the truncated local cipher counter, the received field, and a local block counter. The system then decrypts the data frame based on the local input block and the session key.

Abstract: Autonomous retransmission of data packets onto a network from a Network Interface Card level upon command from a host processor is support. Efficient FIFO buffering in an ASIC is retained. Uses for autonomous retransmission include hardware and software testing and in network management.

Abstract: A circuit and method thereof for arbitrating between a first power source and a second power source in a computer system peripheral device such as a network adapter (e.g., a network interface card) that is connected to multiple power sources. The circuit includes a field effect transistor (FET) and a diode integral with the FET coupled between the first power source and the second power source. The FET is adapted to conduct current from the second power source when power is not available from the first power source, and to substantially prevent current from flowing from the first power source to the second power source. The circuit also includes a voltage regulator coupled between the first power source and the second power source, adapted to regulate voltage such that a voltage from the first power source and a voltage from the second power source are approximately equal.

Abstract: A circuit and method thereof for arbitrating between a plurality of power sources connected to a computer system peripheral device. The circuit includes a first circuit subassembly coupled to a first power source and a second power source. The first circuit subassembly conducts current from the first power source when power is not available from the second power source, and otherwise conducts current from the second power source. The circuit also includes a second circuit subassembly coupled between the first circuit subassembly and a third power source. The second circuit subassembly conducts current from the third power source when the third power source is available and otherwise conducts current from the first circuit subassembly. The second circuit subassembly comprises a first component, a second component and a third component. The first component is coupled to the third power source and the first circuit subassembly.

Abstract: A transmit packet buffer (TPB) is used on a network interface card (NIC) to store downloaded packets and forward them through the media access controller (MAC) and the physical layer interface (PHY) onto the wire. A multi-function TPB is implemented to allow the multiple usage of this buffer. Packets may be downloaded to this buffer through multiple sources. Different types of the packets may each be stored at predefined locations. For example, while the second half of the TPB is used to transmit keep-alive or alert-on-LAN packets, the first half may be used to compare received packets with a wake-up pattern for system wake-up. With multi-function support, various PC management functions may be implemented more effectively and with reduced cost.

Abstract: A circuit and method thereof for indicating availability of a power source other than a first power source in a computer system peripheral device (such as a network adapter) connected to a plurality of power sources including. The circuit includes a circuit subassembly coupled to the first power source and a second power source. The circuit subassembly conducts current from the first power source when power is not available from the second power source and otherwise conducts current from the second power source. A first component is coupled to the circuit subassembly and conducts current when the second power source is available; otherwise, it does not conduct current. A second component is coupled to the circuit subassembly and to the first component. The second component conducts current when the first component is conducting current and otherwise does not conduct current.

Abstract: Support for priority and IP security packets, and other protocols at the network interface level and in conjunction with FIFO-based packet buffers is provided by allowing out of order processing of certain packets in the FIFO. The optimized character of FIFO for sequential transfer is maintained, while particular types of packets are processed out of order to achieve minimum latency and maximum data security in an intelligent network interface card. A buffer stores data packets in an order of receipt. Logic is included in the network interface to transfer packets out of the buffer according to the order of receipt, and according to the respective packet types so that packets having a particular packet type are transferred out of the order of receipt relative to packets having other packet types.

Abstract: A transmit packet buffer device capable of asynchronous read and write functions is used for receiving frame data from a host and forwarding the data over a network. The device comprises dual-ported memory capable of independent write and read access, a plurality of registers for storing address pointers to locations in the memory, and a logic device coupled to the dual-ported memory and the plurality of registers for controlling downloading data into the memory at a first clock speed, and transmitting data from the memory at a second clock speed. The registers are used to store memory addresses for reference by the logic device, and the data is divided into frames.