Abstract: Embodiments of lamp housings for a process chamber are provided herein. In some embodiments, a lamp housing for a process chamber includes: a first plate having a plurality of first openings; a copper plate having a plurality of second openings; a plurality of tubes brazed via a braze alloy to the first plate at first ends of the plurality of tubes and brazed to the copper plate via the braze alloy at second ends of the plurality of tubes, wherein the plurality of tubes have central openings that are aligned with the plurality of first openings and the plurality of second openings, and wherein the braze alloy comprises a nickel containing alloy or a copper containing alloy, wherein the copper containing alloy does not include gold; and an annular jacket circumscribing the plurality of tubes and brazed to the first plate via the braze alloy.

Abstract: A compound includes a polymer associated with a biological agent. The polymer has a first (meth)acryl monomeric unit with a cationic functional group R1 and a second (meth)acryl monomeric unit with a neutral hydrophilic functional group R2. The cationic functional group R1 is chosen from amino groups and alkylamino groups, and the neutral functional group R2 is chosen from polyethylene glycol (PEG), hydroxyl (OH), phosphorylcholine (PC), and mixtures and combinations thereof.

Abstract: Embodiments described herein relate to a faceplate for improving film uniformity. A semiconductor processing apparatus includes a pedestal, an edge ring and a faceplate having distinct regions with differing hole densities. The faceplate has an inner region and an outer region which surrounds the inner region. The inner region has a greater density of holes formed therethrough when compared to the outer region. The inner region is sized to correspond with a substrate being processed while the outer region is sized to correspond with the edge ring.

Abstract: Embodiments described herein relate to a faceplate for improving film uniformity. A semiconductor processing apparatus includes a pedestal, an edge ring and a faceplate having distinct regions with differing hole densities. The faceplate has an inner region and an outer region which surrounds the inner region. The inner region has a greater density of holes formed therethrough when compared to the outer region. The inner region is sized to correspond with a substrate being processed while the outer region is sized to correspond with the edge ring.

Abstract: A management hub is disclosed. The management hub comprises an interface; a master hub controller coupled to the interface; a plurality of ports coupled to the master hub controller; a microcontroller coupled to the master hub controller; and hub setting switch and a slave hub controller coupled to the microcontroller and the plurality of ports. The management hub also includes a memory device coupled to the microcontroller, the memory device including a hidden drive information partition and a hidden drive organizer partition for managing and identifying information in various drives coupled to the plurality of ports, wherein when the management hub is first connected to a host system the drives are displayed in an inactive state.

Abstract: A Flash memory card system is disclosed. The Flash memory card system comprises a Flash memory wireless host adapter and a Flash memory bus wireless device. The Flash memory wireless host adapter comprises a Flash memory card connector and a Flash memory controller coupled to the Flash memory card connector. The Flash-52 memory card signals are converted to standard Flash memory internal bus signals by the Flash memory controller. The host adapter further comprises a Flash memory wireless module coupled to the Flash memory controller for receiving and transmitting the standard Flash memory bus signals wirelessly. The Flash-51 memory bus wireless device comprises a Flash memory bus wireless device adapter coupled to a Flash memory. The device adapter is paired to the wireless module for receiving and transmitting the standard Flash memory bus signals wirelessly. A host device storage capacity utilizing the Flash memory card system is expanded.

Abstract: A management hub is disclosed. The management hub comprises an interface; a master hub controller coupled to the interface; a plurality of ports coupled to the master hub controller; a microcontroller coupled to the master hub controller; and hub setting switch and a slave hub controller coupled to the microcontroller and the plurality of ports. The management hub also includes a memory device coupled to the microcontroller, the memory device including a hidden drive information partition and a hidden drive organizer partition for managing and identifying information in various drives coupled to the plurality of ports, wherein when the management hub is first connected to a host system the drives are displayed in an inactive state.

Abstract: A memory module is disclosed. The memory module comprises a voltage supply; a memory interface coupled to the voltage supply; a plurality of memory components; and a voltage stabilizer converter (VSC) coupled to the memory interface and to the plurality of memory components, the VSC for ensuring that the plurality of memory components operate at their optimum performance level. A voltage stabilizer memory module (VSMM) in accordance with the present invention includes a printed circuit board (PCB) that contains memory chips, discrete components, a voltage stabilizer converter, and other related components. The voltage stabilizer converter uses system voltage supply as its input and its output is the voltage supply for the DRAM components. Accordingly, the VSSM is more adaptable, more stable and has better performance than conventional memory modules.

Abstract: A memory module is disclosed. The memory module comprises a voltage supply; a memory interface coupled to the voltage supply; a plurality of memory components; and a voltage stabilizer converter (VSC) coupled to the memory interface and to the plurality of memory components, the VSC for ensuring that the plurality of memory components operate at their optimum performance level. A voltage stabilizer memory module (VSMM) in accordance with the present invention includes a printed circuit board (PCB) that contains memory chips, discrete components, a voltage stabilizer converter, and other related components. The voltage stabilizer converter uses system voltage supply as its input and its output is the voltage supply for the DRAM components. Accordingly, the VSSM is more adaptable, more stable and has better performance than conventional memory modules.

Abstract: A Flash memory card system is disclosed. The Flash memory card system comprises a Flash memory wireless host adapter and a Flash memory bus wireless device. The Flash memory wireless host adapter comprises a Flash memory card connector and a Flash memory controller coupled to the Flash memory card connector. The Flash-52 memory card signals are converted to standard Flash memory internal bus signals by the Flash memory controller. The host adapter further comprises a Flash memory wireless module coupled to the Flash memory controller for receiving and transmitting the standard Flash memory bus signals wirelessly. The Flash-51 memory bus wireless device comprises a Flash memory bus wireless device adapter coupled to a Flash memory. The device adapter is paired to the wireless module for receiving and transmitting the standard Flash memory bus signals wirelessly. A host device storage capacity utilizing the Flash memory card system is expanded.

Abstract: A method is provided for forming a monolithically integrated optical filter, for example, a Fabry-Perot filter, over a substrate (10). The method comprises forming a first mirror (16) over the substrate (10). A plurality of etalon material layers (32, 34, 36, 38) are formed over the mirror (16), and a plurality of etch stop layers (42, 44, 46) are formed, one each between adjacent etalon material layers (32, 34, 36, 38). A photoresist is patterned to create an opening (54) over the top etalon material layer (38) and an etch (56) is performed down to the top etch stop layer (46). An oxygen plasma (58) may be applied to convert the etch stop layer (46) within the opening (54) to silicon dioxide (57). The photoresist patterning, etching, and applying of an oxygen plasma may be repeated as desired to obtain the desired number of levels (82, 84, 86, 88). A second mirror (72) is then formed on each of the levels (82, 84, 86, 88).

Abstract: A disk drive is disclosed comprising a disk having a plurality of servo sectors defining a plurality of servo tracks, wherein each servo sector comprises a track address identifying a corresponding servo track. A head is actuated over the disk, and a ramp is positioned near an outer diameter of the disk, wherein an edge of the ramp extends over a plurality of the servo tracks. The head is loaded from the ramp onto the disk, and a track address in at least one of the servo sectors is detected and stored. The process is repeated a number of times, and then a starting track proximate an outer diameter of the disk is identified in response to the detected and stored track addresses.

Abstract: The present invention provides methods utilizing the fat-induced antibody response (FIAR) to assess endothelial function. Additional methods are provided that utilize FIAR for diagnosing and monitoring the progression of vascular diseases, the success of treatment for these diseases, and as a measure of the oxidative stress imposed upon vascular endothelium. Still more methods are provided for measuring the oxidation products of lipids in blood following the administration of a polyunsaturated fatty acid (fat-induced acute response) to monitor the treatment success of a vascular disease, for monitoring the degree of endothelial inflammation, and for diagnosing and monitoring the progression of a cardiovascular disease.

Abstract: A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer 14 and etching through the dielectric layer 14 and the organic bonding material 32 with 60CF4/20Ar/60CHF3/20N2. The resist may then be removed with an anisotropic high density oxygen plasma.

Abstract: A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the substrate; and performing (48) an etch to substantially remove the residual layer. Optionally, a patterning layer (52) may be formed on the substrate (12) prior to forming the etch barrier layer (14). Additionally, an adhesive layer (13) may be applied (42) between the substrate (12) and the etch barrier layer (14).

Abstract: A selective etch process for step and flash imprint lithography includes providing (30) a substrate (10); forming (32) a transfer layer (12) on the substrate; forming (34) an etch barrier layer (14) on the transfer layer; patterning (36) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the transfer layer; performing (38) an etch to substantially remove the residual layer; and performing (40) an etch with a mixture of nitrogen and hydrogen, and more preferably NH3, to substantially remove the portion of the transfer layer not underlying the etch barrier layer.

Abstract: Memory modules such as SIMMs and DIMMs are automatically tested by a target-system motherboard such as a PC motherboard. An automated SIMM/DIMM handler is connected to a handler adaptor board that is mounted to the back or solder-side of the PC motherboard. The relatively flat surface of the solder-side of the PC motherboard allows close mounting of the handler. One or more of the SIMM sockets on the motherboard is removed to provide mounting holes for the handler adaptor board. The handler adaptor board provides electrical connection from the module-under-test (MUT) in the handler to the removed SIMM socket on the PC motherboard. The handler adaptor board provides a slight spacing or offset from the solder-side surface of the PC motherboard's substrate, allowing the handler to be plugged directly into tester-connectors on the handler adaptor board.

Abstract: Memory modules such as SIMMs and DIMMs are automatically tested by a target-system motherboard such as a PC motherboard. An automated SIMM/DIMM handler is connected to a handler adaptor board that is mounted to the back or solder-side of the PC motherboard. The relatively flat surface of the solder-side of the PC motherboard allows close mounting of the handler. One or more of the SIMM sockets on the motherboard is removed to provide mounting holes for the handler adaptor board. The handler adaptor board provides electrical connection from the module-under-test (MUT) in the handler to the removed SIMM socket on the PC motherboard. The handler adaptor board provides a slight spacing or offset from the solder-side surface of the PC motherboard's substrate, allowing the handler to be plugged directly into tester-connectors on the handler adaptor board.