Patents by Inventor Ngok Ying Chu
Ngok Ying Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10671323Abstract: A memory system with a shared buffer architecture for multiple decoders reduces transfer latency and power consumption. Such memory system includes a memory device to generate codewords, and a dynamic memory access (DMA) assembly to receive the generated codewords. A first decoding stage of the system comprises a checksum module and a shared memory buffer, including a memory manager and destination ports, that stores and manages codewords received from the DMA assembly. A second decoding stage of the system comprises a bit-flipping (BF) decoder and a min-sum (MS) decoder, each in communication with the shared memory buffer through a respective one of the destination ports. In managing the codewords stored in the shared memory buffer, the memory manager controls assignment including reassignment of the codewords among the destination ports.Type: GrantFiled: August 14, 2018Date of Patent: June 2, 2020Assignee: SK hynix Inc.Inventors: Johnson Yen, Ngok Ying Chu, Abhiram Prabhakar
-
Publication number: 20190065123Abstract: A memory system with a shared buffer architecture for multiple decoders reduces transfer latency and power consumption. Such memory system includes a memory device to generate codewords, and a dynamic memory access (DMA) assembly to receive the generated codewords. A first decoding stage of the system comprises a checksum module and a shared memory buffer, including a memory manager and destination ports, that stores and manages codewords received from the DMA assembly. A second decoding stage of the system comprises a bit-flipping (BF) decoder and a min-sum (MS) decoder, each in communication with the shared memory buffer through a respective one of the destination ports. In managing the codewords stored in the shared memory buffer, the memory manager controls assignment including reassignment of the codewords among the destination ports.Type: ApplicationFiled: August 14, 2018Publication date: February 28, 2019Inventors: Johnson YEN, Ngok Ying CHU, Abhiram PRABHAKAR
-
Patent number: 10122382Abstract: Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch memory and a checksum update unit, the LDPC decoder suitable for, during the first decoding iteration, storing the Lch sign values in the Lch memory of the LDPC decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.Type: GrantFiled: September 19, 2016Date of Patent: November 6, 2018Assignee: SK Hynix Inc.Inventors: Abhiram Prabhakar, Johnson Yen, Ngok Ying Chu
-
Publication number: 20170085276Abstract: Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch memory and a checksum update unit, the LDPC decoder suitable for, during the first decoding iteration, storing the Lch sign values in the Lch memory of the LDPC decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.Type: ApplicationFiled: September 19, 2016Publication date: March 23, 2017Inventors: Abhiram Prabhakar, Johnson Yen, Ngok Ying Chu
-
Patent number: 9564239Abstract: A method for operating a memory controller includes: performing a hard decision read operation to read hard decision data from a memory device; if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages; performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data; performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.Type: GrantFiled: March 16, 2016Date of Patent: February 7, 2017Assignee: SK hynix memory solutions Inc.Inventors: Yu Cai, Johnson Yen, Ngok Ying Chu
-
Publication number: 20160276039Abstract: A method for operating a memory controller includes: performing a hard decision read operation to read hard decision data from a memory device; if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages; performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data; performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.Type: ApplicationFiled: March 16, 2016Publication date: September 22, 2016Inventors: Yu CAI, Johnson YEN, Ngok Ying CHU
-
Patent number: 9189379Abstract: The disclosure is directed to a system for managing data samples utilizing a time division multiplexing controller to allocate time slots for accessing a sample memory according to one or more modes of operation. The time division multiplexing controller is configured to allocate slots for concurrent access by a sample controller, a plurality of detectors, and a noise predictive calibrator when a normal mode is enabled. The time division multiplexing controller is further configured to allocate slots excluding at least one of the sample controller, the plurality of detectors, and the noise predictive calibrator from accessing the sample memory when a retry mode is enabled. In some embodiments, the time division multiplexing controller is further configured to allocate time slots for one or more clients other than the sample controller, the plurality of detectors, and the noise predictive calibrator.Type: GrantFiled: February 6, 2013Date of Patent: November 17, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Herjen Wang, Ngok Ying Chu, Johnson Yen, Lei Chen
-
Publication number: 20140337676Abstract: A data processing system is disclosed including a data detector, a data decoder and a microcontroller. The data detector is operable to apply a data detection algorithm to generate detected values for data sectors. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The microcontroller is operable to configure the data detector and the data decoder to apply the data detection algorithm and the data decode algorithm.Type: ApplicationFiled: July 22, 2013Publication date: November 13, 2014Applicant: LSI CorporationInventors: Johnson Yen, Ngok Ying Chu
-
Publication number: 20140223114Abstract: The disclosure is directed to a system for managing data samples utilizing a time division multiplexing controller to allocate time slots for accessing a sample memory according to one or more modes of operation. The time division multiplexing controller is configured to allocate slots for concurrent access by a sample controller, a plurality of detectors, and a noise predictive calibrator when a normal mode is enabled. The time division multiplexing controller is further configured to allocate slots excluding at least one of the sample controller, the plurality of detectors, and the noise predictive calibrator from accessing the sample memory when a retry mode is enabled. In some embodiments, the time division multiplexing controller is further configured to allocate time slots for one or more clients other than the sample controller, the plurality of detectors, and the noise predictive calibrator.Type: ApplicationFiled: February 6, 2013Publication date: August 7, 2014Applicant: LSI CORPORATIONInventors: Herjen Wang, Ngok Ying Chu, Johnson Yen, Lei Chen
-
Patent number: 8739004Abstract: Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder.Type: GrantFiled: May 10, 2012Date of Patent: May 27, 2014Assignee: LSI CorporationInventors: Sancar K. Olcay, Lei Chen, Madhusudan Kalluri, Johnson Yen, Ngok Ying Chu
-
Publication number: 20130305114Abstract: Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder.Type: ApplicationFiled: May 10, 2012Publication date: November 14, 2013Inventors: Sancar K. Olcay, Lei Chen, Madhusudan Kalluri, Johnson Yen, Ngok Ying Chu
-
Publication number: 20130275827Abstract: Various embodiments of the present invention provide systems and methods for decoding codewords in a multi-section non-binary LDPC decoder. For example, an LDPC decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node messages and to generate variable node to check node messages, and a check node processor operable to process the variable node to check node messages in groups across each of a plurality of sections of an H matrix and to generate the check node to variable node messages.Type: ApplicationFiled: April 12, 2012Publication date: October 17, 2013Inventors: Chung-Li Wang, Lei Chen, Shaohua Yang, Zongwang Li, Herjen Wang, Ngok Ying Chu, Johnson Yen
-
Patent number: 7970962Abstract: A network device includes a port and a bus transmission calculation module. The port is connected to the network device to receive a data burst. The bus transmission calculation module connects to the port for calculating a first number of bytes to be transmitted from a first bus and a second number of bytes to be transmitted from a second bus. The first and second bus connect to the network device and transfer data from the network device.Type: GrantFiled: October 15, 2002Date of Patent: June 28, 2011Assignee: Broadcom CorporationInventors: Ngok Ying Chu, John M. Chiang
-
Patent number: 7194008Abstract: A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.Type: GrantFiled: September 11, 2002Date of Patent: March 20, 2007Assignee: Broadcom CorporationInventors: Ngok Ying Chu, John M. Chiang
-
Patent number: 7058881Abstract: A logic circuit includes an interface and an error detection unit. The interface is configured to receive and transmit a data stream, wherein the data stream includes at least one of a variable length format packet or burst and a fixed length format packet or burst. The error detection unit is configured to detect an error detection code error when a misalignment occurs within the data stream by recursively calculating parity terms.Type: GrantFiled: September 5, 2002Date of Patent: June 6, 2006Assignee: Broadcom CorporationInventor: Ngok Ying Chu
-
Publication number: 20030182613Abstract: A logic circuit includes an interface and an error detection unit. The interface is configured to receive and transmit a data stream, wherein the data stream includes at least one of a variable length burst and a fixed length burst. The error detection unit is configured to detect an error detection code when a misalignment occurs within the data stream by calculating recursive terms.Type: ApplicationFiled: September 5, 2002Publication date: September 25, 2003Applicant: Broadcom CorporationInventor: Ngok Ying Chu
-
Publication number: 20030174736Abstract: A network device includes a port and a bus transmission calculation module. The port is connected to the network device to receive a data burst. The bus transmission calculation module connects to the port for calculating a first number of bytes to be transmitted from a first bus and a second number of bytes to be transmitted from a second bus. The first and second bus connect to the network device and transfer data from the network device.Type: ApplicationFiled: October 15, 2002Publication date: September 18, 2003Applicant: Broadcom CorporationInventors: Ngok Ying Chu, John M. Chiang
-
Publication number: 20030174727Abstract: A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.Type: ApplicationFiled: September 11, 2002Publication date: September 18, 2003Applicant: Broadcom CorporationInventors: Ngok Ying Chu, John M. Chiang