Abstract: A stable binary counter as applicable to synchronous counters, to frequency dividers and more particularly to microwave integrated circuits is constituted by a plurality of elementary counters mounted in cascade. Each elementary counter is formed by a half-adder having two inputs, one "sum" output and one "carry" output. The "sum" output is connected to the input of a master-slave flip-flop, the output of which is connected in a feedback loop to one input of the half-adder. The master and slave flip-flops are controlled by the two complementary waveforms of a single clock signal. The "carry" output of one half-adder is connected to the input of the following half-adder.

Abstract: The invention relates to a coincidence gate, whose output only changes state if the inputs are of the same logic level. It has two parallel-connected NOT circuits, each constituted by a transistor, whose source is at earth and the drain supplied by a resistor, the gates constituting the inputs of the gate. The two resistors are identical saturated resistors and the first NOT circuit is supplied from a fixed voltage, whereas the second NOT circuit is supplied across a Schottky diode connected in the forward direction from the point common to the first saturated resistor and to the drain of the first transistor. The point common to the Schottky diode and the second saturated resistor constitutes the output of the coincidence gate. Application to sequential logic circuits.

Abstract: A circuit is provided for limiting logic voltage deviations in so called very low consumption and ultra high speed DCFL logic circuits. The limiter circuit comprises, mounted in series between a voltage source and ground, a resistor and a normally off field effect transistor. The source of the transistor is grounded. The gate is connected to the drain which forms the output of the limiter circuit. The output voltage, which forms the high logic level, is less than or equal to three times the threshold voltage of the transistor if the current which flows through the load is less than or equal to twice the product of the transconductance of the transistor multiplied by its threshold voltage.

Abstract: A method of manufacturing a logic circuit having at least one field effect transistor connected in series with at least one saturable resistor, wherein an active semiconductor layer is formed with a predetermined thickness on a semi-insulating substrate, ohmic contacts are deposited to produce source and drain regions for the resistor and the transistor, a Schottky contact is deposited between the resistor source and drain ohmic contacts to form a gate region which is then electrically connected to the resistor source contact by means of a metal connection, whereupon the localized thickness of the active layer is measured by measuring the drain-source current to the resistor upon application of a predetermined voltage thereto and a groove then cut between the source and drain contacts of the field effect transistor to obtain a predetermined channel depth from the bottom of the groove to the semi-insulating substrate.

Abstract: A logic circuit including an input stage, wherein a first field-effect transistor is in series with a first saturable resistor interposed on the drain side in the supply of the first transistor, and an output stage including a second transistor which is identical with the first and has a supply on the drain side which is common with the input stage supply. The gate of the second transistor is connected to the drain of the first transistor. The supply circuit of the second transistor is closed across a forward-biased diode, and a second saturable resistor on the ground of the common supply is connected to the source of the first transistor. At least a selected of the field effect transistors or the saturable resistors has a saturable resistor structure formed of a layer of semiconductor material on a semi-insulating substrate. The material is doped to set up a dipolar domain in respect of an electric field which is higher than a so-called critical value.

Abstract: An integrated sequential logic element of the p-n-p-n type (TT.sub.2) having two complementary transistors and forming a flip-flop. The input of the flip-flop is connected to the output of an analog gate (TT.sub.1) having an input controlled by a timing signal (H) permitting the blocking or unblocking thereof and an input (E) receiving a voltage with two levels able to change the flip-flop from one state to the other if the timing signal input is not connected to earth.

Abstract: A random access memory element, fed by a constant current source, contains two complementary transistors forming a pnpn or npnp structure, with a lateral transistor and a transverse transistor. The constant current source is connected to an emitter of the lateral transistor, which is at a distance from its collector. This transistor has a second emitter near this collector, this second emitter receiving a control voltage which is able to trigger the assembly.