Abstract: An apparatus and method used in extracting polysilicon gate doping from C−V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.

Abstract: An interconnection test structure for evaluating more accurately and reliably electromigration characteristics is provided. The test structure includes an elongated metal test conductor having a first end and a second end, small extension metal conductors connected to the first end and the second end of the test conductor, and a plurality of vias disposed in the small extension metal conductors adjacent the first end and the second end of the test conductor. As a result, the current density of the plurality of vias is made to be less than the current density of the test conductor.

Abstract: A categorization of a particular semiconductor wafer based on void size is obtained from sigma data and T0.1% failure data that has been obtained from wafers subjected to isothermal testing. The sigma data and the T0.1% failure data for the particular wafer is compared to stored data corresponding to ranges for sigma and T0.1% data for each of a plurality of void categories, and the particular wafer is categorized based on the stored data. The T0.1% failure data is computed based on a T50% failure data and the sigma value, so that small sample sizes can be utilized to obtain the stored data.

Abstract: A method for detecting damage in a plurality of transistors includes measuring at least one characteristic of the plurality of transistors, applying a constant voltage of a predetermined voltage level for a predetermined period of time, and re-measuring the at least one characteristic of the plurality of transistors, wherein a change in the at least one characteristic indicates damage to the plurality of transistors. In one aspect, the predetermined voltage level is about 9 MV/cm, and the predetermined period of time is about 1 second. In a further aspect, measuring at least one characteristic includes measuring threshold voltage, and the change in the at least one characteristic includes a shift in the threshold voltage.

Abstract: Techniques for measuring process induced damage, such as damage experienced during plasma etching or ion implementation, utilize a differential amplifier having multi-layer antennas (capacitors) of different sizes formed on respective inputs. Measurement of .DELTA.Ids (the difference between Ids.sub.1 and Ids.sub.2 off a MOSFET of the differential pair) or .DELTA.Idlin provides a sensitive and accurate measure of process induced damage. The techniques can be applied to monitor process induced damage while the manufacturing process is ongoing or as a measure of quality of the finished product.

Abstract: A substantially constant current is conducted in a first direction through an interconnect structure having a barrier layer to determine the lifetime of the structure in the first current direction. A substantially identical current is conducted in a second direction through a substantially identical interconnect structure to determine the lifetime of the structure in the second current direction. These tests are repeated for identical structures but having different barrier layer thicknesses. The results of these lifetime tests are compared to determine the barrier layer's effect on electromigration in the structure, which can be used to design the barrier layer to optimize the structure's lifetime and speed.

Abstract: An improved transistor design and methods of construction and testing for same. The novel transistor design method includes the steps of providing a transistor with multiple common gate areas; connecting each gate area to a pad; and adjusting the ratio of the area of the pad to the total of the gate areas to provide a predetermined ratio. The ratio may be adjusted by adjusting the size of the gate, in a single gate implementation, or adjusting the number of gates in a multiple gate configuration. The novel transistor includes a substrate, at least one source disposed on the substrate; at least one drain disposed on the substrate; and at least one gate disposed on the substrate between the source and the drain. The gate has a first layer of at least partially conductive material of area A.sub.g connected to a pad of area A.sub.p. In accordance with the present teachings, the antenna ratio R of the area of the pad A.sub.p to the area of the gate A.sub.g is a predetermined number.