Patents by Inventor Nguyen Phu

Nguyen Phu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210226242
    Abstract: Certain exemplary embodiments can provide a system, which comprises a device. The device comprises a solid electrolyte. The solid electrolyte comprises a reactive nano silicate precursor. The reactive nano silicate precursor is activated by a functional disturber. The functional disturber has a first end that is reactive with a silica/acid composite gel and a second end capable of transporting an ion.
    Type: Application
    Filed: February 19, 2020
    Publication date: July 22, 2021
    Applicant: HK INVENT CORPORATION
    Inventors: Nguyen Khe, Hoai Vo Linh, Nguyen Trinh, Nguyen Tung, Nguyen Phu
  • Publication number: 20200056081
    Abstract: Certain exemplary embodiments can provide a device comprising chemically functionalized graphene. The chemically functionalized graphene comprises a graphene core molecularly doped with functional elements and a subordinate graphene shell. The graphene core has a monolayer structure. The graphene core comprises powdery graphene. The powdery graphene comprises at least one of a graphene hybrid composite, a graphene nano platelet, graphene oxide, and reduced graphene oxide, and a molecular dopant.
    Type: Application
    Filed: August 16, 2018
    Publication date: February 20, 2020
    Applicant: HK INVENT CORPORATION
    Inventors: Nguyen Khe, Nguyen Phu
  • Patent number: 10109587
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: October 23, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
  • Patent number: 9679769
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 13, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund Ramirez Camacho, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Dao Nguyen Phu Cuong, HeeJo Chi
  • Patent number: 9659897
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 23, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Patent number: 9502267
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, includes: a support structure having: an internal insulation layer having a hole, a device connection side, and a removal mark characteristic of a conductive seed layer removed at the device connection side, a first conductive pad in the hole at the device connection side, and an exterior insulation layer over the first conductive pad at the device connection side; an integrated circuit over the exterior insulation layer; and an encapsulation over the integrated circuit.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 22, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Zigmund Ramirez Camacho, Dao Nguyen Phu Cuong
  • Patent number: 9412624
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 9, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
  • Patent number: 9406642
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a plain trace on the substrate; an insulated trace on the substrate; an insulation layer on the insulated trace, the insulation layer at least partially covers the insulated trace; and a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached on the insulated trace, and the plain bump is mounted adjacent to the insulation layer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: HeeJo Chi, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Zigmund Ramirez Camacho, Dao Nguyen Phu Cuong
  • Patent number: 9406531
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund Ramirez Camacho, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Dao Nguyen Phu Cuong, HeeJo Chi
  • Patent number: 9355983
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Patent number: 9331003
    Abstract: An integrated circuit packaging system, and method of manufacture thereof, includes: lead islands; a pre-molded material surrounding a bottom of the lead islands; a device over a portion of the lead islands and having electrical connections to another portion of the lead islands, the electrical connections over areas of the another portion of the lead islands over areas covered by the pre-molded material; and an encapsulation over the device and the lead islands.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 3, 2016
    Assignee: STATS ChipPac Ltd.
    Inventors: Zigmund Ramirez Camacho, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Dao Nguyen Phu Cuong, HeeJo Chi
  • Patent number: 7672317
    Abstract: A method, a system, and network elements for transmitting information between a user equipment and an IP packet gateway, are disclosed, the IP packet gateway communicating with an IP network via an interface, wherein, when the UE is requesting at least one service requiring access to the IP network, authorization of the requested service is checked, wherein an error message is sent from the IP packet gateway to the user equipment, when the requested service is not authorized. The present invention discloses several options of signaling error messages between IP packet gateway and UE, for example, via IP layer signaling (e.g. RESV ERR messages) or link layer signaling (e.g. IS2000 and IOS signaling). The solution according to the present invention, in particular, relates to a CDMA network in connection with an IP multimedia subsystem network.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: March 2, 2010
    Assignee: Nokia Corporation
    Inventors: Ralitsa Gateva, Thinh Nguyen Phu
  • Patent number: 7623504
    Abstract: The present invention relates to a packet data communication system and a method for use in a packet data communication system. The system includes at least one access network configured to provide a wireless interface between a mobile device and the access network for communication of packet data and a core network including at least one core network node for supporting the communication of packet data on the wireless interface. A controller is provided in association with the access network and configured to monitor at least one condition associated with the wireless interface. If the monitoring indicates that the at least one condition is met, the controller sends messages to the core network node in response to messages from the core network node.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: November 24, 2009
    Assignee: Nokia Corporation
    Inventor: Thinh Nguyen Phu
  • Patent number: 5783992
    Abstract: A battery powered sensor in a tire has a microprocessor and a transmitter circuit permanently connected to a battery and a pressure switch or pressure sensor coupled to the microprocessor. The microprocessor has a sleep state and wakes up every few minutes to execute an algorithm which determines on a time basis whether to read the pressure state and transmit a report of significant changes, and determines on a randomly timed basis whether to transmit a status report. A factory test state permits only one signal transmission when the tire is inflated and inhibits other signals for a period to allow testing of many tires without interference from one another.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: July 21, 1998
    Assignee: Delco Electronics Corp.
    Inventors: Todd D. Eberwine, Victor Mendez, Nguyen Phu Nguyen