Abstract: A system and method for monitoring and collecting performance characteristics of a target system and providing the results by way of time-division multiplexing is provided. The performance monitor includes a mechanism for latching a plurality of performance attribute signals. An output circuit, coupled to the latching mechanism, is used to output the latched performance attribute signals in groups, wherein each of the groups is a subset of all of the performance attribute signals. The performance monitor further includes a time division circuit coupled to the output circuit, to allow the output circuit to output each of the groups of performance attribute signals at different times. Each group of performance attribute signals can therefore be transmitted via common output access points, although at different times as the groups are transmitted in succession.

Abstract: A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the storage device. The error-injection system also includes programmable operating modes whereby error injection will occur after every fetch of an associated instruction, or alternatively, after alternate fetches of an associated instruction. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the storage device.