Abstract: An ECL circuit including first and second transistors driven by differential input signals. Both transistors include emitters connected to a common node. The first transistor has a first collector connected to a first output terminal and a first base connected to receive a first biasing signal. The second transistor has a second collector connected to a second output terminal and a second base connected to receive a second biasing signal. The first and second biasing signals driving the first and second transistors are logical complements.

Abstract: An ECL/TTL translation circuit for translating ECL level input signals, which have a high voltage state and a low voltage state, to TTL level output signal, which have a high voltage state and a low voltage state. The translation circuit includes an ECL input circuit, a level shifter, and a TTL output circuit. The ECL input circuit receives the ECL level input signals and generates an intermediate voltage signal corresponding to the ECL level input signal. The level shifter is coupled to the ECL input circuit and maintains the intermediate voltage signal in a desired range of voltages. The TTL output circuit receives the intermediate voltage signal and generates a TTL output signal that corresponds to the intermediate voltage signal and, therefore, corresponds to the ECL input signal.

Abstract: An ECL OR gate circuit, or a logical equivalent AND gate circuit, is provided whereby the input signals are both referenced to the same bias reference signal such that the propagation delay between each input port to the output port of the gate is substantially equivalent. Also provided is an improved ECL flip flop circuit using the ECL OR (or AND) circuit taught in accordance with the teachings of this invention for a faster ECL flip flop. In accordance with the teachings of this invention, a flip flop clock input signal is referenced to the same bias reference signal as the flip flop data input signal such that the propagation delay between the clock input to the output stage is substantially the same as the data input to the output stage.

Abstract: A TTL/ECL translation circuit for translating TTL level input signals, which have a high voltage state and a low voltage state, to ECL level output signals, which have a high voltage state and a low voltage state. The translation circuit includes a TTL input circuit, a level shifter, and an ECL output circuit connected in series. The TTL input circuit receives the TTL level input signals and generates a first intermediate signal, corresponding to the TTL level input signals, that is transmitted to the level shifter. The level shifter receives the first intermediate signal and generates a second intermediate signal corresponding to the first intermediate signal that is transmitted to the ECL output circuit. The ECL output circuit receives the second intermediate signal and generates an ECL output signal corresponding to the second intermediate signal and the TTL input signal.

Abstract: An ECL/TTL translation circuit for translating ECL level input signals, which have a high voltage state and a low voltage state, to TTL level output signal, which have a high voltage state and a low voltage state. The translation circuit includes an ECL input circuit, a level shifter, a TTL output circuit a tristate controller. The ECL input circuit receives the ECL level input signals and generates an intermediate voltage signal corresponding to the ECL level input signal. The level shifter is coupled to the ECL input circuit and maintains the intermediate voltage signal in a desired range of voltages. The TTL output circuit receives the intermediate voltage signal and generates a TTL output signal that corresponds to the intermediate voltage signal and, therefore, corresponds to the ECL input signal. The tristate controller receives the tristate signal and causes the TTL output circuit to enter a high impedance mode when a high level tristate signal is received.

Abstract: A two-level 4:1 ECL multiplexer circuit comprising two 2:1 multiplexer circuits "OR'd" together prior to a shared output stage. A differential Select line, operable at the same voltage level as the input data lines to the 2:1 multiplexer circuits selects one of the input lines to each 2:1 multiplexer circuit. A second Select line, operable at a different voltage level, selects one or the other of the 2:1 multiplexer circuits. This arrangement functions to eliminate an undesirable glitch observed when selecting data inputs in known two-level, 4:1 multiplexers which use emitter dotting.