Abstract: A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.

Abstract: A method of operating a semiconductor device having a plurality of memory cells programmable to a plurality of program states, wherein each of the program states is associated with a range of read currents bounded by a pair of reference read currents, comprising storing data by programming a first memory cell of the plurality of memory cells to a first program state of the plurality of program states, and programming a second memory cell of the plurality of memory cells to a second program state of the plurality of program states; and reading the data by reading the first memory cell to determine a first read current through the first memory cell, reading the second memory cell to determine a second read current through the second memory cell, and comparing the first read current, the second read current and a first one of the reference read currents to each other.

Abstract: In one example, a method comprises storing (n-1) partitions of a first image of code in a first set of banks in single-level cell format, wherein the first set of banks comprise (n-1) of n banks of flash memory cells; and storing (n-1) partitions of the first image and (n-1) partitions of a second image of code in a second set of banks in multi-level cell format, wherein the second set of banks comprise (n-1) of the n banks and the second set of banks comprises a bank not contained in the first set of banks.

Abstract: A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.

Abstract: An EEPROM cell with junction, source and drain regions in a semiconductor substrate. A memory channel region extends between the source and junction regions. A select channel region extends between the drain and junction regions. A floating gate has a first portion disposed over the junction region and insulated therefrom by a first insulation layer, and a second portion disposed over the memory channel region and insulated therefrom by a second insulation layer. A sense gate is disposed over the floating gate. The sense gate wraps around an edge of the first portion without wrapping around an edge of the second portion. A select gate is disposed over the select channel region. The select gate is insulated from the select channel region by a third insulation layer. The third insulation layer is thinner than the second insulation layer and thicker than the first insulation layer.

Abstract: A method of scanning N×N pixels using a vector-by-matrix multiplication array by (a) associating a filter of M×M pixels adjacent first vertical and horizontal edges, (b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups, (c) shifting the filter horizontally by X pixels, (d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines, (e) repeating steps (c) and (d) until a second vertical edge is reached, (f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels, (g) repeating steps (b) through (e) for the vertically shifted filter, and (h) repeating steps (f) and (g) until a second horizontal edge is reached.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.

Abstract: A semiconductor device with interleaved active and isolation regions extending in a first direction. Memory cells formed in the active regions each include first and second drain regions, first and second floating gates, word line gate, first and second control gates, and first and second erase gates. Each of the active regions includes a plurality of first drain contacts each electrically connected to one of the first drain regions in the active region, and a plurality of second drain contacts each electrically connected to one of the second drain regions in the active region. A plurality of first bit lines extend in the first direction and each is electrically connected to the first drain contacts in one of the active regions. A plurality of second bit lines extend in the first direction and each is electrically connected to the second drain contacts in two of the active regions.

Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.

Abstract: A method of forming a semiconductor device, comprising forming insulation material over a semiconductor substrate, forming a conductive contact through the insulation material, forming a lower electrode layer over the insulation material and electrically connected with the conductive contact, forming a resistive switching dielectric material (RSDM) layer directly on the lower electrode layer, forming an upper electrode layer directly on the RSDM layer, selectively removing portions of the upper electrode layer to form a block of the upper electrode layer, selectively removing portions of the RSDM layer to form a block of the RSDM layer disposed under the block of the upper electrode layer, forming insulation spacers on the lower electrode layer and extending along sidewalls of the block of the upper electrode layer and the block of the RSDM layer, and selectively removing portions of the lower electrode layer to form a block of the lower electrode layer.

Abstract: In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a first bit line terminal, a first erase gate terminal, a first control gate terminal, a first floating gate, a word line, a second floating gate, a second control gate terminal, a second erase gate terminal, and a second bit line terminal, wherein the first floating gate can store a first digital or analog value and the second floating gate can store a second digital or analog value; and a bit line decoder for a column to selectively provide a first voltage to the first bit line terminals of non-volatile memory cells in the column and a second voltage to the second bit line terminals of the non-volatile memory cells in the column.

Abstract: A semiconductor device that comprises source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, and a coupling gate having a first portion disposed over the source region and laterally adjacent to a side surface of the floating gate, and a second portion disposed over an upper surface of the floating gate. The coupling gate is insulated from the source region and from the floating gate by an insulation layer having a uniform thickness between the first portion of the coupling gate and the source region, the first portion of the coupling gate and the side surface of the floating gate, and the second portion of the coupling gate and the upper surface of the floating gate.

Abstract: A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.

Abstract: A semiconductor device comprising a first die and a second die. The first die comprises a first substrate, non-planar MOSFET devices formed on the first substrate, and first contact pads electrically connected to the non-planar MOSFET devices. The second die comprises a second substrate, planar MOSFET devices formed on the second substrate, and second contact pads electrically connected to the planar MOSFET devices. Insulation material is formed on the first and second substrates. Contacts are formed on the insulation material. Paths of conductive material extend through the insulation material, and electrically connect to respective ones of the contacts, the first contact pads and the second contact pads.

Abstract: A method comprises forming a first insulation layer on an upper surface of a semiconductor substrate, forming a first conductive layer on the first insulation layer, and forming a compound insulation layer on the first conductive layer, wherein the compound insulation layer comprises a nitride sublayer between a lower oxide sublayer and an upper oxide sublayer. A second insulation layer is formed on the compound insulation layer. A trench is formed that extends through the second insulation layer, the compound insulation layer, the first conductive layer, the first insulation layer, and into the semiconductor substrate. The trench is filled with fill insulation material. The second insulation layer and an upper portion of the fill insulation material are removed. A second conductive layer is formed on the compound insulation layer, and on the fill insulation material in the trench.

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell columns, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.

Abstract: In one example, a system comprises a programmable logic block comprising programmable logic and a configuration block to store and provide configuration data to the programmable logic, the configuration block comprising a flash memory array to store the configuration data, and the flash memory array comprising an array of split-gate flash memory cells.