Abstract: A packaged semiconductor device includes a first semiconductor die including interconnect pads and a seal ring pad surrounding at least some of the interconnect pads, a first portion of an plated seal ring structure formed on the seal ring pad, and a second semiconductor die including a second portion of the plated seal ring structure formed on a major surface of the second semiconductor die. The second portion of the plated seal ring structure is coupled to the first portion of the plated seal ring structure to form a seal around a cavity between the first and second semiconductor die. A plurality of interconnect pillars are on the first major surface of the second semiconductor die. The interconnect pillars are coupled to the interconnect pads on the second semiconductor die.

Abstract: Tin-based wirebond structures and wirebonds formed thereon. In some embodiments, an electronic package includes a semiconductor die located over a substrate and a wire configured to couple a terminal of the semiconductor die to a bond pad on the substrate. A wire bond between the wire and the bond pad may include an amount of tin originated from a layer of tin alloy formed on the bond pad. In other embodiments, a wirebond structure may include a conductive layer and a layer of tin alloy located over a portion of the conductive layer. The layer of tin alloy may provide a wirebonding contact surface configured to receive a bond wire.

Abstract: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

Abstract: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

Abstract: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

Abstract: A packaged integrated circuit includes a die surrounded by an encapsulant in which leads are used to electrically connect the die, which is internal to the encapsulant, externally. The leads have a primary metal that is used for electrical conduction and physical support. The external portion of the lead is coated with another metal, typically tin, that is useful for soldering. This tin layer is formed in a manner that ensures that it is porous. Although porous is generally thought to be a bad characteristic, it turns out to be very effective in absorbing stress and thus retarding whisker growth. Whisker growth, which can short adjacent leads together as well as cause other deleterious effects, has been a major source of failures in packaged integrated circuits. An additional layer of very thin tin that is non-porous can be added before or after the porous tin layer has been deposited.

Abstract: A semiconductor die is housed in a package body. Leads, which are electrically coupled to the semiconductor die, extend from the package body and are for connecting to a printed circuit board or other device. The leads are coated with a material that protects the leads from oxidation. The coating is compatible with solder techniques that are commonly used to attach packaged semiconductors to a printed circuit board. In some examples, the coating is removable, after drying, at temperatures below one hundred eighty degrees Celsius. This allows for solder processes, which are typically at least 180° C., to remove the coating thereby exposing the leads, which has been protected from oxidation, so that it can be soldered to the printed circuit board. In some examples, the coating material includes an organic material. In some examples, the coating material is an organic solderability preservative (OSP).

Abstract: A semiconductor die is housed in a package body. Leads, which are electrically coupled to the semiconductor die, extend from the package body and are for connecting to a printed circuit board or other device. The leads are coated with a material that protects the leads from oxidation. The coating is compatible with solder techniques that are commonly used to attach packaged semiconductors to a printed circuit board. In some examples, the coating is removable, after drying, at temperatures below one hundred eighty degrees Celsius. This allows for solder processes, which are typically at least 180° C., to remove the coating thereby exposing the leads, which has been protected from oxidation, so that it can be soldered to the printed circuit board. In some examples, the coating material includes an organic material. In some examples, the coating material is an organic solderability preservative (OSP).

Abstract: To mitigate mold encapsulant bleeding and solder mask cracking in plastic semiconductor packages, a damming structure constructed from metal traces is formed in-line with the encapsulant perimeter. In one embodiment, each damming trace is connected to only one electrical trace, which includes a bonding connection, a signal portion and a plating portion. The damming traces can consist of one trace that is wider than any of the signal traces or multiple rows of traces, for example. The result is a reduction in mold encapsulant bleeding and, thus, an eradication of the processes performed to clean the bleeding.

Abstract: To mitigate mold encapsulant bleeding and solder mask cracking in plastic semiconductor packages, a damming structure constructed from metal traces is formed in-line with the encapsulant perimeter. In one embodiment, each damming trace is connected to only one electrical trace, which includes a bonding connection, a signal portion and a plating portion. The damming traces can consist of one trace that is wider than any of the signal traces or multiple rows of traces, for example. The result is a reduction in mold encapsulant bleeding and, thus, an eradication of the processes performed to clean the bleeding.

Abstract: A pad area of a substrate (50) includes a conductive trace (52) formed on the substrate (50) having a first surface area, the first surface area being of a first solderability. A conductive pad (56) is formed on the first surface area of the conductive trace (52). The conductive pad (56) has a second surface area, the second surface area being of a second solderability. The second solderability is greater than the first solderability. Because of the different solderabilities, a solder bump (46) on the semiconductor die (40) can be reflowed and connected to the second surface area without using a soldermask (28) to contain the melted solder on the second surface area.