Patents by Inventor Nhon T. Do

Nhon T. Do has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6531774
    Abstract: A test fixture with an isolation plate grounds all of the solder balls of a ball grid array (BGA) of a chip scale package, except for a selected subset of the solder balls, to perform electrical characterization of the package. The isolation plate includes a recess ground into the plate, and a hole in the recess that permits access to the selected subset of solder balls. The recess provides clearance for a fixed compliant probe to land on the solder balls to be tested through the hole, and a probe contact surface for a ground portion of the probe to securely land.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: March 11, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nhon T. Do, John Vu
  • Patent number: 6512675
    Abstract: An intregrated circuit package, which has an intregrated circuit die thereto, is mounted to a system board. The ground trace of the system board is connected to the package, which has a pluality of ground leads on its surface. An electrically conductive epoxy is placed on the ground leads and adheres the package lid to the package board and ground the package lid. A heat sink is mounted to the package lid with an electrically conductive adhesive or electrically conductive slips that extend from a flange of the package lid to a flange of the heat sink to ground the heat sink.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: January 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas S. Tarter, Eric S. Tosaya, Tom J. Ley, Shrikar Bhagath, Nhon T. Do
  • Patent number: 6476625
    Abstract: A method of performing electrical characterization of a chip scale package in which impressionable material, such as copper tape, is applied on a contact surface of an isolation plate of a test fixture. The isolation plate is placed on the tops of an array of electrical contacts of a chip scale package and then pressed against the array of electrical contacts so that at least some of the electrical contacts make an impression in the impressionable material. By examining the impressions in the impressionable material, the coplanarity of the tops of the electrical contacts in the array is determined. This provides a measure of how well grounded the electrical contacts in the array will be when placed in a test fixture with an isolation plate placed on the contacts.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: November 5, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nhon T. Do
  • Patent number: 6424140
    Abstract: A test fixture and method of isolating an electrical contact of chip scale package for testing the electrical characteristics of the electrical contact has a base and an isolation plate. The isolation plate is configured to contact and ground all of the electrical contacts of the chip scale package under test, except for a selected subset of the electrical contacts. The isolation plate includes a hole that provides access to the selected subset of electrical contacts to allow a test probe access to the isolated electrical contact.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: July 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nhon T. Do, Thomas S. Tarter
  • Patent number: 6396296
    Abstract: An integrated circuit package test station supports an integrated circuit package under test in a vertical orientation thereby allowing simultaneous access to both sides of the package. Probe assemblies are utilized on both sides of the package to increase the accuracy, efficiency, and simplicity of performing electrical characterization of the IC package. The IC package holder as well as the probe assemblies are adjustably positioned to allow accurate and precise measurements of through-package electrical characteristics. To aid in positioning the test equipment, a dual-display image magnification system is used which provides images from both sides of the IC package simultaneously.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: May 28, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas S. Tarter, Nhon T. Do
  • Patent number: 6384618
    Abstract: A test fixture with an isolation plate grounds all of the solder balls of a ball grid array (BGA) of a chip scale package, except for a selected subset of the solder balls, to perform electrical characterization of the package. The isolation plate includes at least one hole extending through the isolation plate that exposes the selected subset of the electrical contacts. The hole has a sidewall angled at a non-perpendicular angle from the horizontal plane of the isolation plate. The angle sidewall of the hole provides increased clearance for a fixed compliant probe to land on the solder balls to be tested in an electrical characterization process.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: May 7, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John W. Pursel, John Vu, Nhon T. Do