Abstract: A network device includes an interface (105), a TCP/IP protocol fast processing path (115), and a TCP/IP protocol slow processing path (110). The interface (105) receives a packet and parses the packets to determine a characteristic of the packet. The TCP/IP protocol fast processing path (115) processes the packet if the characteristic of the packet includes a first characteristic. The TCP/IP protocol slow processing path (110) processes the packet if the characteristic of the packet includes a second characteristic.

Abstract: A system and method for efficient reliable execution on a simultaneous multithreading machine. A processor is placed in a reliable execution mode (REM) to detect possible errors during execution of a software application. Only two threads may be configured to operate in this mode. Floating-point store and integer-transfer unary instructions may be converted to new instructions. Each new instruction has two source operands, each corresponding to a different thread is specified by a same logical register number as a single source operand of the original unary instruction. All other instructions are replicated, wherein the original instruction and its twin are assigned to different threads. Simultaneous multi-threaded (SMT) floating-point logic may only be able to provide lockstep execution when it communicates using the new instruction with instantiated integer independent clusters.

Abstract: Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.

Abstract: A network device includes an interface (105), a TCP/IP protocol fast processing path (115), and a TCP/IP protocol slow processing path (110). The interface (105) receives a packet and parses the packets to determine a characteristic of the packet. The TCP/IP protocol fast processing path (115) processes the packet if the characteristic of the packet includes a first characteristic. The TCP/IP protocol slow processing path (110) processes the packet if the characteristic of the packet includes a second characteristic.

Abstract: A network device includes an interface (105), a TCP/IP protocol fast processing path (115), and a TCP/IP protocol slow processing path (110). The interface (105) receives a packet and parses the packets to determine a characteristic of the packet. The TCP/IP protocol fast processing path (115) processes the packet if the characteristic of the packet includes a first characteristic. The TCP/IP protocol slow processing path (110) processes the packet if the characteristic of the packet includes a second characteristic.

Abstract: A system and method for efficient reliable execution on a simultaneous multithreading machine. A processor is placed in a reliable execution mode (REM) to detect possible errors during execution of a mission critical software application. Only two threads may be configured to operate in this mode. Floating-point store and integer-transfer unary instructions may be converted to new binary instructions. Each new instruction has two source operands, each one corresponding to a different thread is specified by a same logical register number as a single source operand of the original unary instruction. All other instructions are replicated, wherein the original instruction and its twin are assigned to different threads. Simultaneous multi-threaded (SMT) floating-point logic may only be able to provide lockstep execution when it communicates using the new instruction with instantiated integer independent clusters.

Abstract: A network device includes an interface (105), a TCP/IP protocol fast processing path (115), and a TCP/IP protocol slow processing path (110). The interface (105) receives a packet and parses the packets to determine a characteristic of the packet. The TCP/IP protocol fast processing path (115) processes the packet if the characteristic of the packet includes a first characteristic. The TCP/IP protocol slow processing path (110) processes the packet if the characteristic of the packet includes a second characteristic.

Abstract: The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.

Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error. In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in a processor including at least one critical memory structure to detect an error and a processor error processing logic hardware coupled to the at least one critical memory structure.

Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error. In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP).

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.

Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP).

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract: A method of detecting errors in a datapath in accordance with the invention includes generating a plurality of electronic signals, computing a first at least one data-signature value based, at least in part, on the plurality of electronic signals and staging the plurality of electronic signals and the first at least one data-signature value. The method further includes transmitting the plurality of electronic signals via at least one intervening stage of circuitry, computing a second at least one data-signature value based, at least in part, on the plurality of electronic signals, and comparing the first at least one data-signature value the said second at least one data-signature value.

Abstract: The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.

Abstract: Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log.

Abstract: The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.

Abstract: Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.

Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP).

Abstract: An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.