Patents by Inventor Nhon Toai Quach
Nhon Toai Quach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418936Abstract: Techniques for providing execution verification at an integrated circuit device are described. The integrated circuit device may include a processor core configured to execute instructions. The integrated circuit device may also include a trace block configured to extract an execution trace from the processor core, the execution trace indicating the instructions that have been executed by the processor core. The integrated circuit device may further include a verification core configured to receive the execution trace from the trace block, extract an address from a control transfer instruction in the execution trace, perform one or more checks on the address, and generate an alarm signal based on the one or more checks.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Ali Rahbar, Nhon Toai Quach, Samatha Gummalla, John Charles Wright, Jonathan Kang, Utpal Vijaysinh Solanki, Gururaj Ananthateerta
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Publication number: 20230418985Abstract: Techniques for providing remote attestation at an integrated circuit device are described. The integrated circuit device may include a memory. The integrated circuit device may also include a write bitmap comprising a bitmap that tracks the write addresses of detected memory write operations to the memory. The integrated circuit device may further include a security subsystem configured to send one or more address ranges of interest to the write bitmap and obtain a bitmap status from the write bitmap indicating that a write address within the one or more address ranges of interest was detected.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Ali Rahbar, Nhon Toai Quach, Samatha Gummalla, Diana Chang, Donghyun Choi, Utpal Vijaysinh Solanki, Gururaj Ananthateerta
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Publication number: 20190171941Abstract: An electronic device comprises a data transmitting interface configured to transmit data, a memory configured to store the data, a processor configured to execute an application program, and an accelerator coupled to the processor via a bus. According to an operation request transmitted from the processor, the accelerator reads the data from the memory, performs an operation to the data to generate computed data, and stores the computed data in the memory. The electronic device can improve computational efficiency. An accelerator and an accelerating method applicable to a neural network operation are also provided.Type: ApplicationFiled: November 29, 2018Publication date: June 6, 2019Inventors: Nhon-Toai QUACH, Chung-Chieh CHEN, Kong-Qiao WANG, Wen-Fu TSAI, Tzu-Wei YEH, Chung-Hao CHENG, Hui-Min LU
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Patent number: 9632562Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.Type: GrantFiled: February 8, 2015Date of Patent: April 25, 2017Assignee: QUALCOMM INCORPORATEDInventors: Nhon Toai Quach, Virat Deepak, Oscar Cabral Arias, Yanru Li, Haw-Jing Lo, Michael Drop, Venkata Narayana Ramesh Pinnamaraju Durga, Moinul Khan
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Patent number: 9563369Abstract: Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.Type: GrantFiled: April 14, 2014Date of Patent: February 7, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Nhon Toai Quach, Susan Carrie, Jeffrey Andrews, John Sell, Kevin Po
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Publication number: 20160196231Abstract: Various embodiments of methods and systems for managing bus bandwidth allocation in a system on a chip are disclosed. Certain embodiments monitor a high speed bus for a measurement window of time to identify valid bits uniquely associated with transaction requests issued by a master processing engine. The method continues to monitor the bus over the window to identify completed transactions. A latency value is calculated by subtracting a target latency from an actual latency for each completed transaction. The latency value is aggregated in a counter. At the conclusion of the window, if the aggregated latency value is positive, the method may conclude that the average latency per transaction over the window exceeded the target latency per transaction and that the bandwidth allocated to the engine should be increased.Type: ApplicationFiled: January 7, 2015Publication date: July 7, 2016Inventors: NHON TOAI QUACH, JEAN-MARIE QUOC DANH TRAN, NIKOLAI SCHLEGEL, JEAN-LOUIS TARDIEUX, BING XIAO
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Publication number: 20160148670Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.Type: ApplicationFiled: February 8, 2015Publication date: May 26, 2016Inventors: NHON TOAI QUACH, VIRAT DEEPAK, OSCAR CABRAL ARIAS, YANRU LI, HAW-JING LO, MICHAEL DROP, VENKATA NARAYANA RAMESH PINNAMARAJU DURGA, MOINUL KHAN
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Publication number: 20160077959Abstract: A computing device and methods for exposing a solid-state non-volatile memory element to multiple masters in a computing device are disclosed. A portion of a solid-state non-volatile memory element includes code and data for use by a non-boot processing resource. A host controller in communication with the solid-state non-volatile memory element is modified to receive and respond to a resource identifier unique to the processing resource that is requesting read access to the solid-state non-volatile memory element. Logic executed by a boot master and logic executed by a non-boot processing resource are synchronized in response to a set of indicators.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: NHON TOAI QUACH, YANRU LI, WILLIAM EDWARD KIMBERLY
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Publication number: 20150293709Abstract: Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.Type: ApplicationFiled: April 14, 2014Publication date: October 15, 2015Applicant: Microsoft CorporationInventors: Nhon Toai Quach, Susan Carrie, Jeffrey Andrews, John Sell, Kevin Po
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Patent number: 7376877Abstract: A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.Type: GrantFiled: April 13, 2004Date of Patent: May 20, 2008Assignee: Intel CorporationInventors: Nhon Toai Quach, John Fu, Sunny Huang, Jeen Miin, Dean Mulla
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Patent number: 6948094Abstract: Processor implementation-specific instructions save a processor state in a system memory and attempt to correct the error. Control is then transferred to processor-independent instructions. Control is returned to the processor implementation-specific instructions which then return to an interrupted context of the processor by restoring the processor state.Type: GrantFiled: September 28, 2001Date of Patent: September 20, 2005Assignee: Intel CorporationInventors: Len Schultz, Nhon Toai Quach, Dean Mulla, Jim Hays, John Fu
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Patent number: 6895527Abstract: A method of handling memory errors. A memory fault indication is received that is true if an error in the memory is detected while executing a memory load request to retrieve a value from the memory. A speculative load indication is received that is true if the memory load request was issued speculatively. If the memory fault indication is true and the speculative load indication is true, then an error indication that the returned value is invalid is provided, otherwise, error recovery is performed.Type: GrantFiled: September 30, 2000Date of Patent: May 17, 2005Assignee: Intel CorporationInventors: Nhon Toai Quach, Len Schultz
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Publication number: 20040199851Abstract: A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.Type: ApplicationFiled: April 13, 2004Publication date: October 7, 2004Inventors: Nhon Toai Quach, John Fu, Sunny Huang, Jeen Miin, Dean Mulla
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Patent number: 6772383Abstract: A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol and an error correction code. The error correction code provides error correction for a third symbol that includes the first symbol and the second symbol.Type: GrantFiled: May 27, 1999Date of Patent: August 3, 2004Assignee: Intel CorporationInventors: Nhon Toai Quach, John Fu, Sunny Huang, Jeen Miin, Dean Mulla
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Patent number: 6631489Abstract: A cache memory includes a plurality of lines of memory and a plurality of cache coherency state registers. Each of the plurality of cache coherency state registers is associated with one of the plurality of lines of memory. Each of the plurality of cache coherency state registers further includes four elements having one of a first value and a second value to form a four bit code for a MESI Protocol. The four bit code provides a first set of codes having a minimum distance of two from every other code, and a second set of codes having a minimum distance of three from every other code. The first set of codes includes a first code representing an Invalid state, a second code representing a Shared state, and a third code representing an Exclusive state. The second set of codes includes a fourth code representing a Modified state.Type: GrantFiled: October 29, 2002Date of Patent: October 7, 2003Assignee: Intel CorporationInventors: Nhon Toai Quach, Sunny Huang
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Patent number: 6567952Abstract: An apparatus includes a plurality of error detection circuits. Each of the plurality of error detection circuits is coupled to one of a like plurality of ways in a set associative cache memory to receive a tag word and an error detection flag from the coupled way. Each of the plurality of error detection circuits generates a way error signal that is asserted if an error is detected in the tag word of the coupled way. A logical OR circuit is coupled to the plurality of error detection circuits to receive the plurality of way error signals. The logical OR circuit generates a tag error signal that is asserted if at least one of the plurality of way error signals is asserted.Type: GrantFiled: April 18, 2000Date of Patent: May 20, 2003Assignee: Intel CorporationInventors: Nhon Toai Quach, Gregory S. Mathews
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Publication number: 20030074601Abstract: Processor implementation-specific instructions save a processor state in a system memory and attempt to correct the error. Control is then transferred to processor-independent instructions. Control is returned to the processor implementation-specific instructions which then return to an interrupted context of the processor by restoring the processor state.Type: ApplicationFiled: September 28, 2001Publication date: April 17, 2003Inventors: Len Schultz, Nhon Toai Quach, Dean Mulla, Jim Hays, John Wai Cheong Fu
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Publication number: 20030066012Abstract: A cache memory includes a plurality of lines of memory and a plurality of cache coherency state registers. Each of the plurality of cache coherency state registers is associated with one of the plurality of lines of memory. Each of the plurality of cache coherency state registers further includes four elements having one of a first value and a second value to form a four bit code for a MESI Protocol. The four bit code provides a first set of codes having a minimum distance of two from every other code, and a second set of codes having a minimum distance of three from every other code. The first set of codes includes a first code representing an Invalid state, a second code representing a Shared state, and a third code representing an Exclusive state. The second set of codes includes a fourth code representing a Modified state.Type: ApplicationFiled: October 29, 2002Publication date: April 3, 2003Inventors: Nhon Toai Quach, Sunny Huang
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Patent number: 6505318Abstract: A method and an apparatus for receiving partially error protected data. A transmission of a binary code is received. The binary code is selected from a first set of codes having a first minimum distance from every other code and a second set of codes having a second minimum distance from every other code. The second minimum distance is greater than the first minimum distance. A first single bit error in the transmission is detected if the transmission is a distance of one unit from one of the codes in the second set of codes.Type: GrantFiled: October 1, 1999Date of Patent: January 7, 2003Assignee: Intel CorporationInventors: Nhon Toai Quach, Sunny Huang