Patents by Inventor Ni-Wan Fan

Ni-Wan Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210224460
    Abstract: A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Fong-Yuan CHANG, Jyun-Hao CHANG, Sheng-Hsiung CHEN, Ho Che YU, Lee-Chung LU, Ni-Wan FAN, Po-Hsiang HUANG, Chi-Yu LU, Jeo-Yen LEE
  • Publication number: 20210225838
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Inventors: Ni-Wan Fan, Jung-Chan Yang, Hsiang-Jen Tseng, Tommy Hu, Chi-Yu Lu, Wei-Ling Chang
  • Patent number: 10985160
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ni-Wan Fan, Jung-Chan Yang, Hsiang-Jen Tseng, Tommy Hu, Chi-Yu Lu, Wei-Ling Chang
  • Patent number: 10970450
    Abstract: A semiconductor device comprising active areas and a structure. The active areas are formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions; The active areas are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and of the second row includes a corresponding first and second number predetermined number of the first tracks. The structure has at least two contiguous rows including: at least one instance of the first row; and at least one instance of the second row. In the first direction, the instance(s) of the first row have a first width and the instance(s) of the second row a second width substantially different than the first width.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Ho Che Yu, Lee-Chung Lu, Ni-Wan Fan, Po-Hsiang Huang, Chi-Yu Lu, Jeo-Yen Lee
  • Patent number: 10923426
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Publication number: 20200243446
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions within a substrate. A gate structure is over the substrate between the first and second source/drain regions. A middle-end-of-the-line (MEOL) structure is over the second source/drain region. The MEOL structure has a bottommost surface that continuously extends in a first direction from directly contacting a top of the second source/drain region to laterally past an outer edge of the second source/drain region. A conductive structure is on the MEOL structure. A second gate structure is separated from the gate structure by the second source/drain region. The conductive structure continuously extends in a second direction over the MEOL structure and past opposing sides of the second gate structure. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the MEOL structure along through the conductive structure.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Patent number: 10672708
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Publication number: 20190393219
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Inventors: Ni-Wan Fan, Jung-Chan Yang, Hsiang-Jen Tseng, Tommy Hu, Chi-Yu Lu, Wei-Ling Chang
  • Patent number: 10446546
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. A first active semiconductor region is disposed in a first vertical level of the semiconductor structure. A second active semiconductor region is disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction. A first conductive structure is disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ni-Wan Fan, Jung-Chan Yang, Hsiang-Jen Tseng, Tommy Hu, Chi-Yu Lu, Wei-Ling Chang
  • Publication number: 20180350743
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 6, 2018
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Patent number: 10128234
    Abstract: A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ni-Wan Fan, Sheng-Hsiung Chen, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Chi-Yu Lu
  • Publication number: 20180150592
    Abstract: A semiconductor device comprising active areas and a structure. The active areas are formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions; The active areas are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and of the second row includes a corresponding first and second number predetermined number of the first tracks. The structure has at least two contiguous rows including: at least one instance of the first row; and at least one instance of the second row. In the first direction, the instance(s) of the first row have a first width and the instance(s) of the second row a second width substantially different than the first width.
    Type: Application
    Filed: October 12, 2017
    Publication date: May 31, 2018
    Inventors: Fong-Yuan CHANG, Jyun-Hao CHANG, Sheng-Hsiung CHEN, Ho Che YU, Lee-Chung LU, Ni-Wan FAN, Po-Hsiang HUANG, Chi-Yu LU, Jeo-Yen LEE
  • Publication number: 20180145070
    Abstract: A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Ni-Wan Fan, Sheng-Hsiung Chen, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Chi-Yu Lu
  • Publication number: 20180138171
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. A first active semiconductor region is disposed in a first vertical level of the semiconductor structure. A second active semiconductor region is disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction. A first conductive structure is disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 17, 2018
    Inventors: Ni-Wan Fan, Jung-Chan Yang, Hsiang-Jen Tseng, Tommy Hu, Chi-Yu Lu, Wei-Ling Chang
  • Publication number: 20170154848
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.
    Type: Application
    Filed: June 1, 2016
    Publication date: June 1, 2017
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu