Abstract: Examples may include a method of power aware load balancing in a computing platform. The method includes computing a number of enabled worker cores to process an expected traffic of received packets. A number of active consumer queues is adjusted based at least in part on the number of enabled worker cores, with consumer queues being associated with worker cores. A worker core polls the consumer queue associated with the worker core, gets and processes a packet descriptor describing a received packet from the consumer queue based on the consumer queue being not empty, and enters a low power state when the consumer queue is empty and pends on a new packet descriptor being entered into the consumer queue.

Abstract: Technologies for moving workloads between hardware queue managers include a compute device. The compute device includes a set of hardware queue managers. Each hardware queue manager is to manage one or more queues of queue elements and each queue element is indicative of a data set to be operated on by a thread. The compute device also includes circuitry to execute a workload with a first hardware queue manager of the set of hardware queue managers, determine whether a workload migration condition is present, determine whether a second hardware queue manager of the set of hardware queue managers has sufficient capacity to manage a set of queues associated with the workload, move, in response to a determination that the second hardware queue manager does have sufficient capacity, the workload to the second hardware queue manager, and reduce, after the move of the workload to the second hardware queue manager, a power usage of the first hardware queue manager.

Abstract: Technologies for inflight packet count limiting include a network device. The network device is to receive a packet from a producer application. The packet is configured to be enqueued into a packet queue as a queue element to be consumed by a consumer application. The network device is also to increment, in response to receipt of the packet, an inflight count variable, determine whether a value of the inflight count variable satisfies an inflight count limit, and enqueue, in response to a determination that the value of the inflight count variable satisfies the inflight count limit, the packet.

Abstract: Generally discussed herein are systems, devices, and methods for network security monitoring (NSM). A hardware queue manager (HQM) may include an input interface to receive first data from at least a first worker thread, queue duplication circuitry to generate a copy of at least a portion of the first data to create first copied data, and an output interface to (a) provide the first copied data to a second worker thread, and/or (b) provide at least a portion of the first data to a third worker thread.

Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

Abstract: Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.

Abstract: An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Abstract: Various embodiments are generally directed to techniques to distribute encrypted packets among multiple cores in a load-balanced manner for further processing. An apparatus may include a processor component; a decryption component to decrypt an encrypted packet to generate a decrypted packet from the encrypted packet, the encrypted packet comprising a header that comprises at least one field of information; a hash component to generate a header hash from the at least one field of information during decryption of at least a portion of the encrypted packet by the decryption component, the header hash comprising a smaller quantity of bits than the at least one field of information; and a distribution component to select a first core of multiple cores coupled to the processor component based on the header hash and to transmit the decrypted packet to the first core from the processor component. Other embodiments are described and claimed.

Abstract: Various embodiments are generally directed to techniques to distribute encrypted packets among multiple cores in a load-balanced manner for further processing. An apparatus may include a processor component; a decryption component to decrypt an encrypted packet to generate a decrypted packet from the encrypted packet, the encrypted packet comprising a header that comprises at least one field of information; a hash component to generate a header hash from the at least one field of information during decryption of at least a portion of the encrypted packet by the decryption component, the header hash comprising a smaller quantity of bits than the at least one field of information; and a distribution component to select a first core of multiple cores coupled to the processor component based on the header hash and to transmit the decrypted packet to the first core from the processor component. Other embodiments are described and claimed.

Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.

Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.

Abstract: An apparatus and method includes receiving frames from multiple channels, each frame partitioned into multiple timeslots, reading a timeslot lookup table including an entry that specifies an assignment associated with each timeslot, and storing the data associated with a particular timeslot in a memory location based on the assignment.

Abstract: Systems and methods are disclosed for using High-level Data Link Control (HDLC) channel context information to simultaneously process multiple HDLC channels. Preferred embodiments of the present invention enable a single network processing engine to process multiple HDLC channels. The current state of the HDLC channel can be evaluated, stored, and restored, which means that the processing of a channel can be halted, the channel state read and stored, and the state of a different channel written to the processing engine. This allows the engine to begin processing a new channel, and then, at a later stage, restore the state of the original channel and resume processing.

Abstract: According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of stages associated with the instruction to be executed and the number of stages associated with the subsequent instruction is provided.

Abstract: According to some embodiments, storage registers are provided for a processor pipeline.

Abstract: According to some embodiments, stall optimization is provided for a processor pipeline.

Abstract: According to some embodiments, storage registers are provided for a processor pipeline.