Abstract: In one embodiment, an apparatus includes a plurality of processing cores, where each processing core is capable of executing at least one of a subset of an instruction set architecture (ISA). The apparatus also includes hardware circuitry to determine, during runtime, whether a thread comprising instructions of a particular ISA subset can execute on a particular processing core, and based on the determination, indicate a capability of the thread to be executed on the particular processing core in subsequent executions.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. An example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. The example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. The example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. The example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.

Abstract: Methods, apparatus, and computer programs are disclosed for buffer management in load balancing. In one embodiment, a method is disclosed to comprise providing a set of buffers by a storage of a load balancer to store packets to be distributed by the load balancer, and distributing the packets by the load balancer to a set of cores of a computer processor to be processed by the set of cores. The method further comprises responsive to buffer utilization in the storage over a first threshold, obtaining by circuitry of the load balancer, from top of a memory stack coupled to the storage, additional buffers to store the packets to be distributed and responsive to buffer utilization in the storage below a second threshold, returning by the circuitry of the load balancer, available buffers in the storage to the top of the memory stack.

Abstract: An example of an apparatus may include a first cache organized as two or more portions, a second cache, and circuitry coupled to the first cache and the second cache to determine a designated portion allocation for data transferred from the first cache to the second cache, and track the designated portion allocation for the data transferred from the first cache to the second cache. Other examples are disclosed and claimed.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Abstract: Methods and apparatus to assign and check anti-replay sequence numbers. In one embodiment, a method includes assigning, by circuitry, sequence numbers to packets of traffic flows, wherein a first sequence number is assigned to a first packet based on a determination that the first packet is within a first traffic flow mapped to a first secure channel, and wherein the first sequence number is within a set of sequence numbers allocated to the first secure channel and maintained by the circuitry. The method continues with allocating the packets of traffic flows to be processed among a plurality of processor cores and processing the packets of traffic flows by the plurality of processor cores.

Abstract: An accelerator device may generate and submit descriptors to be processed by the accelerator device. Software executing on a processor may submit descriptors to the accelerator device to be processed in parallel.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Abstract: Examples relate to an apparatus, device, method, and computer program for processing a sequence of units of data, and of a computer program comprising such an apparatus or device.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Abstract: Various embodiments are generally directed to techniques to distribute encrypted packets among multiple cores in a load-balanced manner for further processing. An apparatus may include a processor component; a decryption component to decrypt an encrypted packet to generate a decrypted packet from the encrypted packet, the encrypted packet comprising a header that comprises at least one field of information; a hash component to generate a header hash from the at least one field of information during decryption of at least a portion of the encrypted packet by the decryption component, the header hash comprising a smaller quantity of bits than the at least one field of information; and a distribution component to select a first core of multiple cores coupled to the processor component based on the header hash and to transmit the decrypted packet to the first core from the processor component. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor for queue selection includes a plurality of processing engines (PEs) to execute threads, and a hardware queue manager. The hardware queue manager is to: detect that a first class lacks valid requests to be scheduled, the first class comprising a first plurality of scheduling queues, the first class associated with a first credit count; select a second class based on a second credit count associated with the second class, the second class comprising a second plurality of scheduling queues; and in response to a selection of the second class based on the second credit count, select a queue in the selected second class. Other embodiments are described and claimed.

Abstract: Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

Abstract: Particular embodiments described herein provide for a communication system that can be configured for receiving, at an electronic device, data related to one or more wireless access points visible to the electronic device, communicating the data related to the one or more wireless access points to a network element, and receiving an approximate distance to one or more points of interest from the electronic device.

Abstract: Particular embodiments described herein provide for a communication system that can be configured for receiving, at an electronic device, data related to one or more wireless access points visible to the electronic device, communicating the data related to the one or more wireless access points to a network element, and receiving an approximate distance to one or more points of interest from the electronic device.

Abstract: Various embodiments are generally directed to techniques to distribute encrypted packets among multiple cores in a load-balanced manner for further processing. An apparatus may include a processor component; a decryption component to decrypt an encrypted packet to generate a decrypted packet from the encrypted packet, the encrypted packet comprising a header that comprises at least one field of information; a hash component to generate a header hash from the at least one field of information during decryption of at least a portion of the encrypted packet by the decryption component, the header hash comprising a smaller quantity of bits than the at least one field of information; and a distribution component to select a first core of multiple cores coupled to the processor component based on the header hash and to transmit the decrypted packet to the first core from the processor component. Other embodiments are described and claimed.

Abstract: Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

Abstract: A weakly ordered doorbell at least reduces the cycle cost of talking to a device. This may manifest as simple performance improvement, but it also allows a reduction in the number of jobs batched into a single doorbell—current DPDK (Data Plane Development Kit) code (for example) batches larger numbers of packets behind a single doorbell to amortize the per-packet doorbell cost. Reducing the number of packets at least provide a better latency profile.

Abstract: In some embodiments a memory controller receives a signal indicating a power condition of a system. In response to the received signal the memory controller controls a clock enable signal to a memory, allows only already issued memory controller signals to finish, and forces the memory into a self refresh. A transition is made such that power is only provided to the memory controller and to the memory, and no power is provided to any other components in the system. Other embodiments are described and claimed.