Abstract: A network chip includes a main control chip and an off-chip memory. The main control chip includes an on-chip memory configured to cache a message entering the network chip; a flow classification module configured to map the message in the on-chip memory to at least one piece of flow table information; a flow recognizing module configured to recognize a potential flow that is a possible target flow in the information flow according to the at least one piece of flow table information, and output the flow table information corresponding to the potential flow to the off-chip memory to be accumulated; and a flow screening module configured to read the flow table information corresponding to the potential flow accumulated in the off-chip memory when a set trigger condition is met, and recognize a target flow in the potential flow based on the read flow table information.

Abstract: Provided is a Field Programmable Gate Array (FPGA) application merging system for multiple platforms of a same series, which is used in a testing or manufacturing system comprising an adapter and at least two platforms. The FPGA application merging system comprises: at least two functional modules corresponding to the at least two platforms respectively; an IO selector connected to the at least two functional modules respectively, configured to select one of the at least two functional modules adaptively; and an IO attribute controller connected to the IO selector, configured to select an attribute in accordance with the selected functional module, wherein each IO has a three-state logic attribute. The FPGA application merging system may significantly reduce the cost of the FPGA version in later development, maintenance, storage, upgrading and so on, mitigate the difficulty of storage, loading and other operations on the board, and significantly increase the operation efficiency.