Patents by Inventor Nianging Zhang

Nianging Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Modeling delays for small nets in an integrated circuit design
    Patent number: 6587999
    Abstract: A method of modeling delays in an integrated circuit design is disclosed that may be used to reduce the computation time of path delays in an integrated circuit design. A method of modeling delays in an integrated circuit design includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: July 1, 2003
    Assignee: LSI Logic Corporation
    Inventors: Lei Chen, Sandeep Bhutani, Nianging Zhang