Abstract: A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

Abstract: A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.