Abstract: Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.

Abstract: Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.

Abstract: Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.

Abstract: Circuits and methods for a mixer circuit involve having a first transistor with first and second terminals, where the first terminal is configured to handle an input RF signal. The mixer has a second transistor including a first terminal coupled to the second terminal of the first transistor, a second terminal configured to handle an input oscillator signal, and a third terminal configured to output an intermediate frequency (IF) signal. The IF signal includes a mixed product of the input RF signal and the input oscillator signal. A gate oxide thickness of the first transistor is less than a gate oxide thickness of the second transistor to provide enhanced linearity and a low noise figure. One or more of the mixers can be implemented in a receiver design.

Abstract: A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer.