Abstract: A circuit for extracting the square root of a 2n-bit input binary number. The circuit comprises n successive subcircuits, the m.sup.th such subcircuit consisting of (m+1) add/subtract cells, where 1.gtoreq.m.ltoreq.n. The successive subcircuits process successively less significant pairs of bits of the input number, such bits respectively being received on a data input of two respective add/subtract cells in each subcircuit. Such cells receive a logic bit "1" on a second data input and a logic "0" on a control input thereof, and so always operate in the addition mode. The remaining add/subtract cells of any m.sup.th subcircuit are controlled by the carry signal which constitutes the output of the (m-1).sup.th subcircuit. The root extraction circuit thereby effects subtraction by 2's complement addition, avoiding the need for inversion of any data input signals. That achieves a completely regular circuit pattern permitting more efficient use of chip area when the circuit is realized in integrated form.