Abstract: A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria.

Abstract: A matrix access system having a plurality of columns, comprising a plurality of circuits each being adapted for selectively accessing one of said columns; an interface, communicating data with said plurality of circuits; at least one redundant circuit, adapted for selectively accessing each of said columns and communicating data with said interface; a test circuit, for comparing data communicated by a respective one of said circuits and said redundant circuit; and means for selectively logically replacing a respective circuit with said redundant circuit.

Abstract: A matrix access system having a plurality of columns, comprising a plurality of circuits each being adapted for selectively accessing one of said columns; an interface, communicating data with said plurality of circuits; at least one redundant circuit, adapted for selectively accessing each of said columns and communicating data with said interface; a test circuit, for comparing data communicated by a respective one of said circuits and said redundant circuit; and means for selectively logically replacing a respective circuit with said redundant circuit.