Patents by Inventor Nicholas A. Oleksinski

Nicholas A. Oleksinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Generic methodology to support chip level integration of IP core instance constraints in integrated circuits
    Patent number: 7669155
    Abstract: A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: February 23, 2010
    Assignee: LSI Corporation
    Inventors: Balaji Ganesan, David Vinke, Ekambaram Balaji, Nicholas A. Oleksinski
  • Generic methodology to support chip level integration of IP core instance constraints in integrated circuits
    Publication number: 20080244491
    Abstract: A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Applicant: LSI Logic Corporation
    Inventors: Balaji Ganesan, David Vinke, Ekambaram Balaji, Nicholas A. Oleksinski
  • Timing constraint generator
    Patent number: 7062736
    Abstract: A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: June 13, 2006
    Assignee: LSI Logic Corporation
    Inventors: Nicholas A. Oleksinski, Michael A. Minter
  • Timing constraint generator
    Publication number: 20040268279
    Abstract: A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.
    Type: Application
    Filed: June 24, 2003
    Publication date: December 30, 2004
    Applicant: LSI LOGIC CORPORATION
    Inventors: Nicholas A. Oleksinski, Michael A. Minter