Abstract: A method of testing an integrated circuit design includes the steps of providing a logical model of an integrated circuit, having a plurality of data ports, providing at least two simulators, the first simulator coupled to a first data port of the integrated circuit model, and the second simulator coupled to a second different data ports of said integrated circuit model. The further includes the steps of providing an instruction stream to the first and second simulators, the instruction stream including at least two instruction threads corresponding to the at least two simulators, the simulators providing signals to the data ports in accordance with instructions provided from each of the instruction threads. In addition, the method further includes the step of delaying the first simulator from processing its corresponding instruction thread until dependencies between instruction threads have been satisfied.

Abstract: A reliable diagnostic system for running power-up diagnostics, displaying power-up diagnostic results, and retaining a power system status history. First, a method of testing a processor module in a computer system is provided. A processor including a serial port reads processor module diagnostic test instructions from a PROM in a serial line controller through the serial port by way of a serial bus in response to power-up reset instructions. Next, a reliable connection of a serial control bus to the modules is provided. Accordingly, backplane connectors are provided including wide signal conducting elements having multiple solder connection points to the modules and backplane. The serial control bus is electrically connected to each module through the multiple connection points of these signal conducting elements. Also, an apparatus and method for indicating module failures in a computer system is provided.

Abstract: A method of testing an integrated circuit having a plurality of pins includes the steps of providing a functional test set having an ordered group of test strings wherein each element of the test string is related to one of the pins of said integrated circuit. The group of test strings is searched to locate a sequence of test strings having a undesirable pattern. The undesirable pattern can be a pattern in which none of the elements associated with the test string changes or a pattern in which a reference element and at least one other element of the test string changes. When a sequence of test strings having the undesirable pattern is located, the group of test strings is processed to correct the undesirable pattern. When all the vector sequences having an undesirable patterns are corrected, the group of test vectors is applied to the input pins of the integrated circuit.

Abstract: A reliable diagnostic system for running power-up diagnostics, displaying power-up diagnostic results, and retaining a power system status history. First, a method of testing a processor module in a computer system is provided. A processor including a serial port reads processor module diagnostic test instructions from a PROM in a serial line controller through the serial port by way of a serial bus in response to power-up reset instructions. Next, a reliable means for connecting a serial control bus modules is provided. Accordingly, backplane connectors are provide including wide signal conducting elements having multiple solder connection points to the modules and backplane. The serial control bus is electrically connected to each module through the multiple connection points of these signal conducting elements. Also, an apparatus and method for indicating module failures in a computer system is provided.

Abstract: A cache memory exchange protocol that utilizes an exchange memory access request is provided A cache controller issues the exchange request over a system bus to a main memory in response to a cache miss if the cache location is dirty. Upon receiving the request, the main memory decodes the request and fetches a block of information desired by the transfers a dirty cache block of information over the system bus and stores the dirty block in a temporary register located in the main memory. The block of information desired by the CPU is thereafter transferred by the main memory to the CPU via the system bus. The dirty cache block residing in the temporary register is then stored in the main memory storage elements.