Abstract: An apparatus including a system bus coupled to an I/O interface which includes a pointer register and a rejecting circuit which determines whether a write to the pointer register will be accepted or rejected. The I/O interface is further coupled to at least one I/O bus having at least one I/O device connected thereto. The system bus is further coupled to a main memory and to a Central Processing Unit (CPU) which is capable of executing software instructions, providing a command structure corresponding to an access of an I/O device, and writing to the pointer register an address of a location in main memory of the command structure. The CPU further includes a hardware indicator responsive to the rejecting circuit for providing a status signal indicating the status of a write to the pointer register. The CPU executes the software in accordance with the status signal. The apparatus allows the software being executed by the CPU to software pend accesses to devices not directly connected to the system bus.

Abstract: The invention provides a new process and apparatus for generating and selectively processing command requests issued over a bus. Command requests are generated by devices, each of which may be authorized or not authorized to cause the execution of the requested command. A unique identifier is provided for each device. The command requests are received and the identity of the device which issued the command request is determined. The command is then executed only if the unique identifier associated with the requesting device indicates that the device is authorized to cause the execution of the requested command.