Patents by Inventor Nicholas B. Peterson
Nicholas B. Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9385728Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal.Type: GrantFiled: October 13, 2014Date of Patent: July 5, 2016Assignee: Intel CorporationInventors: Choupin Huang, Vijaya K. Boddu, Stefan Rusu, Nicholas B Peterson
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Publication number: 20150188548Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal.Type: ApplicationFiled: October 13, 2014Publication date: July 2, 2015Inventors: Choupin Huang, Huang K. Boddu, Stefan Rusu, Nicholas B. Peterson
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Publication number: 20150085458Abstract: Inductive coupling arising between adjacent vias in interconnect technologies (commonly associated with printed circuit boards or package) can be combatted through the addition of metal plates to vias. The plates generate capacitive coupling that can compensate for the inductive crosstalk normally generated between vias in printed circuit boards or packages. When the added plates of two neighboring vias overlap with each other, a capacitive coupling is generated. By balancing the inductive coupling with capacitive coupling, an effective reduction of far end crosstalk may be obtained.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Inventors: Raul Enriquez Shibayama, Mauro Lai, Richard K. Kunze, Nicholas B. Peterson, Carlos A. Lizalde Moreno, Kai Xiao
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Patent number: 8860479Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal.Type: GrantFiled: June 27, 2013Date of Patent: October 14, 2014Assignee: Intel CorporationInventors: Choupin Huang, Vijaya K. Boddu, Stefan Rusu, Nicholas B Peterson
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Publication number: 20140266340Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal.Type: ApplicationFiled: June 27, 2013Publication date: September 18, 2014Inventors: CHOUPIN HUANG, VIJAYA K. BODDU, STEFAN RUSU, NICHOLAS B. PETERSON
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Patent number: 6055372Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic.Type: GrantFiled: May 1, 1997Date of Patent: April 25, 2000Assignee: Intel CorporationInventors: James Kardach, Sung Soo Cho, Nicholas B. Peterson, Thomas R Lane, Jayesh M. Joshi, Neil Songer
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Patent number: 5671421Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic.Type: GrantFiled: December 7, 1994Date of Patent: September 23, 1997Assignee: Intel CorporationInventors: James Kardach, Sung Soo Cho, Nicholas B. Peterson, Thomas R. Lane, Jayesh M. Joshi, Neil Songer
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Patent number: 5535420Abstract: A computer architecture which provides for the dynamic configuration of peripheral interrupts. A global router is implemented for mapping interrupts received over a multiple-line shared interrupt bus to correspond to system standard IRQ interrupt signals for a programable interrupt controller (PIC). The global router may configure interrupts to be both level sensitive and edge-triggered interrupts as well as being sharable among multiple devices. The global router further provides its interrupts to a shared interrupt bus which may receive other system interrupts for propagation to the computer system's PIC. The global router provides a centrally located motherboard resource that provides a totally flexible interrupt configuration scheme.Type: GrantFiled: December 14, 1994Date of Patent: July 9, 1996Assignee: Intel CorporationInventors: James Kardach, Sung S. Cho, Nicholas B. Peterson, Thomas R. Lane