Abstract: An inertial sensing system comprises a first multi-axis atomic inertial sensor, a second multi-axis atomic inertial sensor, and an optical multiplexer optically coupled to the first and second multi-axis atomic inertial sensors. The optical multiplexer is configured to sequentially direct light along different axes of the first and second multi-axis atomic inertial sensors. A plurality of micro-electrical-mechanical systems (MEMS) inertial sensors is in operative communication with the first and second multi-axis atomic inertial sensors. Output signals from the first and second multi-axis atomic inertial sensors aid in correcting errors produced by the MEMS inertial sensors by sequentially updating output signals from the MEMS inertial sensors.

Abstract: An inertial sensing system comprises a first multi-axis atomic inertial sensor, a second multi-axis atomic inertial sensor, and an optical multiplexer optically coupled to the first and second multi-axis atomic inertial sensors. The optical multiplexer is configured to sequentially direct light along different axes of the first and second multi-axis atomic inertial sensors. A plurality of micro-electrical-mechanical systems (MEMS) inertial sensors is in operative communication with the first and second multi-axis atomic inertial sensors. Output signals from the first and second multi-axis atomic inertial sensors aid in correcting errors produced by the MEMS inertial sensors by sequentially updating output signals from the MEMS inertial sensors.

Abstract: A complementary (Al,Ga)As/GaAs heterostructure insulated gate field-effect transistor (HIGFET) approach is described in which both the n-channel and p-channel transistors utilize a two-dimensional electron (hole) gas in undoped high mobility channels to form planar, complementary GaAs-based integrated circuits.

Abstract: A self-aligned gate process for integrated circuits based on modulation doped (Al, Ga)As/GaAs field effect transistors and in which the regions on each side of the metal silicide gate are heavily ion implanted to form the low resistance regions on either side of the gate.

Abstract: The gated Transmission Line Model (GTLM) structure is a novel characterization device and measurement tool for integrated circuit process monitoring. This test structure has Schottky gates between the ohmic contacts of a TLM pattern. The gate lengths are varied and the gate-to- ohmic separations are kept constant to provide an accurate determination of several important FET channel parameters. It offers a precise method for measuring the FET source resistance which requires no parameter fitting and which works equally well on planar, self-aligned gate, and recessed gate FET's. In addition, the GTLM structure offers the only available means to measure sheet resistance of enhancement-mode FET channels. The gated-TLM structure can also be used to find the effective free surface potential. The structure may be combined with capacitance-voltage analysis or geometric magnetoresistance analysis to create mobility and doping profile of actual FET channels.