Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract: Microphone assemblies may be provided that have microelectromechanical systems microphones and associated application-specific integrated circuits mounted to printed circuit boards. The application-specific integrated circuits may contain amplifier circuitry for amplifying microphone signals from the microphone. One or more though-silicon vias may be formed in the application-specific integrated circuit that serve as an acoustic port through which sound may pass. The application-specific integrated circuit may be embedded in the printed circuit board and the microphone may be mounted to the upper surface of the printed circuit board, the application-specific integrated circuit and microphone may be stacked on the upper surface of the printed circuit board, or the microphone and application-specific integrated circuit may be mounted to the printed circuit board so that the microphone is received within an opening in the printed circuit board.

Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract: Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

Abstract: Systems and methods for providing early hinting to nonvolatile memory charge pumps are disclosed. Charge pumps associated with one or more nonvolatile memory dies can be proactively activated based on a determination that a command queue of access requests contains at least a threshold number of consecutive access requests of the same type. Based on analysis of the command queue, the memory controller can transmit an early hint command to a nonvolatile memory die to proactively activate its charge pump to provide a voltage suitable for executing the consecutive access requests of the same type.

Abstract: Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget.

Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Abstract: Systems and methods are disclosed for managing the peak power consumption of a system, such as a non-volatile memory system (e.g., flash memory system). The system can include multiple subsystems and a controller for controlling the subsystems. Each subsystem may have a current profile that is peaky. Thus, the controller may control the peak power of the system by, for example, limiting the number of subsystems that can perform power-intensive operations at the same time or by aiding a subsystem in determining the peak power that the subsystem may consume at any given time.

Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Abstract: Systems and methods for providing early hinting to nonvolatile memory charge pumps are disclosed. Charge pumps associated with one or more nonvolatile memory dies can be proactively activated based on a determination that a command queue of access requests contains at least a threshold number of consecutive access requests of the same type. Based on analysis of the command queue, the memory controller can transmit an early hint command to a nonvolatile memory die to proactively activate its charge pump to provide a voltage suitable for executing the consecutive access requests of the same type.

Abstract: Systems and methods are disclosed for power management of a system having non-volatile memory (“NVM”). One or more controllers of the system can optimally turn modules on or off and/or intelligently adjust the operating speeds of modules and interfaces of the system based on the type of incoming commands and the current conditions of the system. This can result in optimal system performance and reduced system power consumption.

Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Abstract: Microphone assemblies may be provided that have microelectromechanical systems microphones and associated application-specific integrated circuits mounted to printed circuit boards. The application-specific integrated circuits may contain amplifier circuitry for amplifying microphone signals from the microphone. One or more though-silicon vias may be formed in the application-specific integrated circuit that serve as an acoustic port through which sound may pass. The application-specific integrated circuit may be embedded in the printed circuit board and the microphone may be mounted to the upper surface of the printed circuit board, the application-specific integrated circuit and microphone may be stacked on the upper surface of the printed circuit board, or the microphone and application-specific integrated circuit may be mounted to the printed circuit board so that the microphone is received within an opening in the printed circuit board.

Abstract: A data storage device comprises a data storage medium and a connector that provides an interface between the data storage medium and a host device. The connector has a shape that substantially conforms to an internal storage interconnect standard. The connector comprises a first set of electrical contacts that substantially conform to the internal storage interconnect standard, and a second set of contacts configured to provide connectivity with the host device in accordance with an external storage interconnect standard. Also described are cables for connecting the data storage device to a host via the external storage interconnect standard as well as an interconnect detector.

Abstract: A data storage device comprises a data storage medium; an interface between the data storage medium and a host device configured to provide connectivity according to a plurality of storage interconnect standards. The data storage device also includes a interconnect detector configured to determine the presence of a physical connection to the host device and identify an interconnect standard of the host device, wherein the interconnect standard of the host device is one of the plurality of storage interconnect standards; and a controller configured to: receive an indication of the interconnect standard of the physical connection from the interconnect detector, receive data access commands in accordance with the interconnect standard from the host device via the connector; process the data access commands by accessing the data storage medium; and send a response to the data access commands in accordance with the interconnect standard to the host via the connector.

Abstract: A data storage device comprises a data storage medium; an interface between the data storage medium and a host device configured to provide connectivity according to a plurality of storage interconnect standards. The data storage device also includes a interconnect detector configured to determine the presence of a physical connection to the host device and identify an interconnect standard of the host device, wherein the interconnect standard of the host device is one of the plurality of storage interconnect standards; and a controller configured to: receive an indication of the interconnect standard of the physical connection from the interconnect detector, receive data access commands in accordance with the interconnect standard from the host device via the connector; process the data access commands by accessing the data storage medium; and send a response to the data access commands in accordance with the interconnect standard to the host via the connector.

Abstract: A data storage device comprises a data storage medium and a connector that provides an interface between the data storage medium and a host device. The connector has a shape that substantially conforms to an internal storage interconnect standard. The connector comprises a first set of electrical contacts that substantially conform to the internal storage interconnect standard, and a second set of contacts configured to provide connectivity with the host device in accordance with an external storage interconnect standard. Also described are cables for connecting the data storage device to a host via the external storage interconnect standard as well as an interconnect detector.