Abstract: Methods, systems, and techniques for performing blockchain-enabled atomic settlement. A first instruction, which includes a first leg specifying a first counterparty and a second counterparty that are counterparties to a first transaction and an amount of a first asset owned by the first counterparty, is obtained. The first instruction is confirmed to be authorized; this involves locking the first asset without transferring the first asset in response to obtaining that confirmation. The first instruction is executed after the first instruction is confirmed to be authorized. Executing the first instruction involves transferring the first asset from the first counterparty to the second counterparty. That the first instruction has been executed is recorded in a blockchain.

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Abstract: A dynamically matched mixer system (200) for use in a direct conversion radio frequency (RF) receiver includes a frequency generator (201, 203, 205) that includes plurality of dividers (407) for providing differential local oscillator reference sources (FLO+ and FLO?) and mitigation frequency reference sources (F1 and F2) from reference oscillator (205). A mixer (209) mixes the differential local oscillator reference sources (FLO+ and FLO?) and the mitigation frequency reference sources (F1 and F2) while dynamic matching units (211, 213) are used for receiving the mitigation frequency reference sources and matching switching parameters of differential input signals (IRF+ and IRF?) and differential baseband output signals (IBB+ and IBB?).

Abstract: A frequency generator (10) includes a direct digital synthesizer (14) having an accumulator (18 or 28) for providing an interim output and a digital interpolator (16) for interpolating the interim output to provide an output signal with reduced electromagnetic interference. The digital interpolator can include at least one converter among a digital-to-phase converter (22) or a digital-to-time converter (32). The frequency generator can further include a digitally programmable spreading function (12) applied to an input of the direct digital synthesizer.

Abstract: A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A frequency generator (10) includes a direct digital synthesizer (14) having an accumulator (18 or 28) for providing an interim output and a digital interpolator (16) for interpolating the interim output to provide an output signal with reduced electromagnetic interference. The digital interpolator can include at least one converter among a digital-to-phase converter (22) or a digital-to-time converter (32). The frequency generator can further include a digitally programmable spreading function (12) applied to an input of the direct digital synthesizer.