Abstract: A system for firmware protection and validation includes: a memory device, including firmware; a chipset, a microprocessor; a secure logic device in electrical communication with the chipset and the memory device; and a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset, when the hold signal is applied to the chipset, the power on reset circuit de-asserts the reset signal, when the reset signal is de-asserted, the secure logic device validates the content of the firmware in the memory device, and further wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the hold signal applied to the chipset.

Abstract: A system for providing write-protection functionality to a memory device includes: a memory device including configurable registers controlling write and erase operations in the memory device; a system interface; a filter logic device in electrical communication with the memory device and further in communication with the system interface; and a power on reset circuit in communication with the system interface and the filter logic device, wherein the power on reset circuit asserts a reset signal to the system interface on startup of the system, further wherein, while the reset signal is asserted to the system interface, the filter logic device modifies the configurable registers to prevent all further write and erase operations to the memory device and then the power on reset circuit de-asserts the reset signal to the system interface enabling communication between the system interface and the memory device.

Abstract: A system for firmware protection and validation includes: a memory device, including firmware; a chipset, a microprocessor; a secure logic device in electrical communication with the chipset and the memory device; and a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset, when the hold signal is applied to the chipset, the power on reset circuit de-asserts the reset signal, when the reset signal is de-asserted, the secure logic device validates the content of the firmware in the memory device, and further wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the hold signal applied to the chipset.

Abstract: A system for providing write-protection functionality to a memory device includes: a memory device including configurable registers controlling write and erase operations in the memory device; a system interface; a filter logic device in electrical communication with the memory device and further in communication with the system interface; and a power on reset circuit in communication with the system interface and the filter logic device, wherein the power on reset circuit asserts a reset signal to the system interface on startup of the system, further wherein, while the reset signal is asserted to the system interface, the filter logic device modifies the configurable registers to prevent all further write and erase operations to the memory device and then the power on reset circuit de-asserts the reset signal to the system interface enabling communication between the system interface and the memory device.