Abstract: A memory control interface is provided for use with at least one external memory device used in conjunction with a microprocessor based system of the type providing address, control and data signals and having a basic input/output operating system for providing predefined instructions. The memory control interface apparatus receives the address, control and data signals from the microprocessor based system. Decoder circuitry decodes the received signals to identify predetermined signals corresponding to the predefined instructions. Timing circuitry responsive to the identified predetermined signals produces timing signals. Enabling circuitry responsive to both the identified predetermined signals and the timing signals generates an enable signal for coupling the microprocessor based system and the external memory; only after reliable operation of the microprocessor based system is identified.