Patents by Inventor Nicholas E. Bofferding

Nicholas E. Bofferding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170249231
    Abstract: A computer system may identify a source code for a program. The source code may include one or more instructions. The computer system may then receive a selection of two or more assessment metrics for evaluating the source code. The computer system may then generate an assessment score for each instruction in the source code based on the two or more assessment metrics. The computer system may then provide an assessment score indicator to for each instruction in the source code.
    Type: Application
    Filed: February 29, 2016
    Publication date: August 31, 2017
    Inventors: Nicholas E. Bofferding, Andrew Geissler, Michael C. Hollinger
  • Publication number: 20170199737
    Abstract: Systems, methods, and computer program products to perform an operation comprising identifying a first commit of a plurality of commits for a software project, wherein a source code of the first commit is executable in a first system architecture, computing a score for each commit in a first set of the plurality of commits, wherein each score reflects a likelihood of success in porting the source code of the respective commit from the first system architecture to a second system architecture, wherein a version of each commit in the first set of commits is between a version of the first commit and a current version of the software project, identifying one or more of the first set of commits based on the scores for each commit, and building the source code of the one or more of the first set of commits for execution on the second system architecture.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Inventors: Nicholas E. BOFFERDING, Andrew J. GEISSLER, Michael C. HOLLINGER, Ted M. PACYGA
  • Publication number: 20170091072
    Abstract: A computer-implemented method and system for assessing risk of a software program and software updates to a program to prioritize verification resources, which includes receiving code for a software product for a testing assessment. The code is analyzed according to a risk assessment criteria, and the risk assessment criteria includes risk assessment factors. The risk assessment factors for the code are weighted as part of the criteria. A risk assessment score of the code is determined based on the criteria. Testing resources are allocated in response to the risk assessment score.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Balaji V. Atyam, Nicholas E. Bofferding, Andrew Geissler, Michael C. Hollinger
  • Publication number: 20170091078
    Abstract: A computer-implemented method and system for assessing risk of a software program and software updates to a program to prioritize verification resources, which includes receiving code for a software product for a testing assessment. The code is analyzed according to a risk assessment criteria, and the risk assessment criteria includes risk assessment factors. The risk assessment factors for the code are weighted as part of the criteria. A risk assessment score of the code is determined based on the criteria. Testing resources are allocated in response to the risk assessment score.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 30, 2017
    Inventors: Balaji V. Atyam, Nicholas E. Bofferding, Andrew Geissler, Michael C. Hollinger
  • Patent number: 8819691
    Abstract: A mechanism, in a data processing system, is provided for logical partition defragmentation. The mechanism gathers resource requirements for a plurality of logical partitions running in a plurality of power domains within one or more servers. The mechanism determines optimal hardware utilization for the plurality of logical partitions. The mechanism migrates one or more of the plurality of logical partitions to run in a subset of the plurality of power domains such that at least one power domain within the plurality of power domains is unused. The mechanism puts the at least one unused power domain in a low power state.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anis M. Abdul, Nicholas E. Bofferding, Ajay K. Mahajan, Rashmi Narasimhan
  • Patent number: 8819693
    Abstract: A mechanism, in a data processing system, is provided for logical partition defragmentation. The mechanism gathers resource requirements for a plurality of logical partitions running in a plurality of power domains within one or more servers. The mechanism determines optimal hardware utilization for the plurality of logical partitions. The mechanism migrates one or more of the plurality of logical partitions to run in a subset of the plurality of power domains such that at least one power domain within the plurality of power domains is unused. The mechanism puts the at least one unused power domain in a low power state.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anis M. Abdul, Nicholas E. Bofferding, Ajay K. Mahajan, Rashmi Narasimhan
  • Publication number: 20120284549
    Abstract: A mechanism, in a data processing system, is provided for logical partition defragmentation. The mechanism gathers resource requirements for a plurality of logical partitions running in a plurality of power domains within one or more servers. The mechanism determines optimal hardware utilization for the plurality of logical partitions. The mechanism migrates one or more of the plurality of logical partitions to run in a subset of the plurality of power domains such that at least one power domain within the plurality of power domains is unused. The mechanism puts the at least one unused power domain in a low power state.
    Type: Application
    Filed: May 4, 2011
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anis M. Abdul, Nicholas E. Bofferding, Ajay K. Mahajan, Rashmi Narasimhan
  • Publication number: 20120284484
    Abstract: A mechanism, in a data processing system, is provided for logical partition defragmentation. The mechanism gathers resource requirements for a plurality of logical partitions running in a plurality of power domains within one or more servers. The mechanism determines optimal hardware utilization for the plurality of logical partitions. The mechanism migrates one or more of the plurality of logical partitions to run in a subset of the plurality of power domains such that at least one power domain within the plurality of power domains is unused. The mechanism puts the at least one unused power domain in a low power state.
    Type: Application
    Filed: April 30, 2012
    Publication date: November 8, 2012
    Applicant: International Business Machines Corporation
    Inventors: Anis M. Abdul, Nicholas E. Bofferding, Ajay K. Mahajan, Rashmi Narasimhan
  • Publication number: 20120110665
    Abstract: A computer implemented method monitors activity within a device driver layer of a computer. An arrival rate is identified within a device driver for the node. The arrival rate is a rate at which packets arrive at a network adapter of the node from all other nodes within a network. If the arrival rate exceeds at least one threshold, the node undergoes a state change. The at least one threshold delineates between a plurality of states for the node.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 3, 2012
    Applicant: International Business Machines Corporation
    Inventors: Anis M. Abdul, Nicholas E. Bofferding, Nikhil Hegde, Ajay K. Mahajan, Rashmi Narasimhan
  • Patent number: 8001287
    Abstract: During an initial generation/assignment of location codes for field replaceable units (FRUs) that are and/or may be attached to the computer system, the service processor provides an alias location code for each FRU not currently attached. When the service processor later detects a concurrent install of the FRU, the service processor's firmware generates the correct location code from data retrieved from the FRU, and replaces the alias location code stored within the service processor's internal data structures with the correct location code. The firmware also forwards the correct location code back to a serviceability application, and the application utilizes the new location code in all remaining concurrent install commands to maintain a single, consistent view of the system.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Nicholas E. Bofferding, Erlander Lo, Kanisha Patel
  • Patent number: 7558874
    Abstract: A method of reducing Ethernet power consumption in a network having an operating system by reducing an Ethernet link speed to a minimum rate required for current data link traffic, and automatically commanding an Ethernet adapter/cable to decrease or increase a link rate by dynamically auto-negotiating an Ethernet port by IEEE standards to a lower or higher link rate without user intervention.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: July 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Sivarama K. Kodukula, Omar Cardona, James B. Cunningham, Binh K. Hua, Nicholas E. Bofferding
  • Publication number: 20080155368
    Abstract: During an initial generation/assignment of location codes for field replaceable units (FRUs) that are and/or may be attached to the computer system, the service processor provides an alias location code for each FRU not currently attached. When the service processor later detects a concurrent install of the FRU, the service processor's firmware generates the correct location code from data retrieved from the FRU, and replaces the alias location code stored within the service processor's internal data structures with the correct location code. The firmware also forwards the correct location code back to a serviceability application, and the application utilizes the new location code in all remaining concurrent install commands to maintain a single, consistent view of the system.
    Type: Application
    Filed: October 10, 2006
    Publication date: June 26, 2008
    Inventors: Nicholas E. Bofferding, Erlander Lo, Kanisha Patel
  • Publication number: 20080133962
    Abstract: A method of preventing failed field replaceable units (FRUs) directly connected to an interprocessor bus or fabric from interfering with the operation of a computer system during concurrent maintenance operations. When a FRU fails a concurrent maintenance operation, the service processor stores identification information corresponding to the failed FRU in an alert fail registry or a hot add fail registry and reports the failure status to a user. When a user attempts to perform a new concurrent maintenance operation on a FRU, the service processor compares that FRU to the alert fail registry or the hot add fail registry. If a concurrent maintenance operation on the requested FRU would cause a system crash due to interference with the failed FRU, the service processor notifies the repair and verify application (which notifies the user) and prevents concurrent maintenance operations from occurring on the new FRU.
    Type: Application
    Filed: December 4, 2006
    Publication date: June 5, 2008
    Inventors: Nicholas E. Bofferding, Erlander Lo, Kanisha Patel, Timothy A. Smith