Abstract: An example embodiment includes a liquid crystal on silicon (LCOS) system. The LCOS system includes multiple pixels, a pixel voltage supply source (voltage source), an external buffer, and a local buffer. The voltage source is configured to supply an analog ramp to the pixels. The external buffer is configured to buffer the voltage source from the pixels. The local buffer is configured to buffer the external buffer from a subset of pixels of the plurality of pixels.

Abstract: An example embodiment includes a LCOS IC. The LCOS IC includes multiple pixels, a column driver, and multiple conductive lines. The pixels are arranged in a pixel array. The column driver is configured to supply multiple signals to a column of pixels included in the pixel array. Each of the conductive lines couples the column driver to a subset of pixels in the column of pixels. The conductive lines are configured such that two or more of the signals can be supplied to two or more of the subsets of pixels with some overlapping duration.

Abstract: An example embodiment includes a liquid crystal on silicon (LCOS) system. The LCOS system includes multiple pixels, a pixel voltage supply source (voltage source), an external buffer, and a local buffer. The voltage source is configured to supply an analog ramp to the pixels. The external buffer is configured to buffer the voltage source from the pixels. The local buffer is configured to buffer the external buffer from a subset of pixels of the plurality of pixels.

Abstract: An example embodiment includes a LCOS IC. The LCOS IC includes multiple pixels, a column driver, and multiple conductive lines. The pixels are arranged in a pixel array. The column driver is configured to supply multiple signals to a column of pixels included in the pixel array. Each of the conductive lines couples the column driver to a subset of pixels in the column of pixels. The conductive lines are configured such that two or more of the signals can be supplied to two or more of the subsets of pixels with some overlapping duration.

Abstract: An example embodiment includes a liquid crystal on silicon (LCOS) system. The LCOS system includes multiple pixels, a pixel voltage supply source (voltage source), an external buffer, and a local buffer. The voltage source is configured to supply an analog ramp to the pixels. The external buffer is configured to buffer the voltage source from the pixels. The local buffer is configured to buffer the external buffer from a subset of pixels of the plurality of pixels.

Abstract: An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.

Abstract: An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.