Abstract: A first component is soldered to a second component by placing the first component on the second component with solder therebetween, then ultrasonically vibrating at least one of the first and second components to thereby tack the solder to at least one of the first and second components, and by reflowing the solder. Ultrasonic vibration of at least one of the first and second components to thereby tack the solder is preferably performed for less than one second. A component placer places the first component on the second component with solder therebetween. An ultrasonic vibrator ultrasonically vibrates at least one of the placed first and second components, to thereby tack the solder to at least one of the placed first and second components. A solder reflower reflows the tacked solder to thereby solder the first component to the second component.

Abstract: A fluxless soldering sample pretreating system includes a sample chamber having an opening therein and a sample holder. A sample chamber extension extends outwardly from the opening to define a passageway from the sample chamber extension, through the opening, and into the sample chamber. A fluorine-containing gas is supplied into the sample chamber extension. Am energy source such as a microwave oven surrounds the sample chamber extension. The microwave oven produces microwave energy in the sample chamber extension to form a plasma therein and dissociate the fluorine-containing gas into atomic fluorine. A perforated aluminum plate extends transversely across the passageway and blocks the plasma from traversing the passageway from the sample chamber extension into the sample chamber, while allowing the atomic fluorine to traverse the passageway from the sample chamber extension into the sample holder.

Abstract: A temporary substrate for solder bumps may be used to transfer solder bumps to a microelectronic device. The temporary substrate includes a solder nonwettable surface and a plurality of conductive vias therein. A solder bump is formed on each of the conductive vias and is electrically and mechanically connected thereto. The solder bump extends over the solder nonwettable surface to produce a solder bump cross-sectional area which is greater than the cross-sectional area of the conductive via. A microelectronic device is placed adjacent the temporary substrate with each input/output pad adjacent a respective solder bump. An electrical and mechanical connection is formed between the solder bump and the input/output pad, and the microelectronic device is separated from the temporary substrate with the solder bump remaining connected to the input/output pad. The temporary substrate can also be used for burn-in and testing of microelectronic devices and rework on multichip modules.

Abstract: An electrical connector includes a housing and a row of connector contacts coupled to the housing. The row of connector contacts has a predetermined center-to-center spacing between adjacent contacts, with the predetermined center-to-center spacing being relatively large relatively far from an imaginary reference point in the row of connector contacts, and being relatively small relatively near the imaginary reference point in the row of connector contacts. The imaginary reference point is preferably at the center of the row of contacts, and the center-to-center contact spacing preferably progressively increases from the center of the row to the ends of the row. The size of the connector contacts may also progressively increase as well. The electrical connector is preferably adapted for use with a multilayer ceramic substrate which includes a row of capture pads of the same predetermined center-to-center spacing at the edge thereof.

Abstract: A method of soldering a copper layer without the use of fluxing agents by exposing the copper layer to a fluorine-containing plasma. Solder is then placed onto the surface of the copper layer and reflowed. Reflow can take place at low temperatures, atmospheric pressure and in an inert or oxidizing atmosphere using standard solder reflow equipment.

Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.

Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.

Abstract: Capture pads of variable size are provided on the face of a multilayer ceramic substrate, to accommodate the actual shrinkage tolerance of the substrate at each capture pad position. For example, assuming a minimum shrinkage reference point is at the center of the substrate face, the capture pad size is relatively large adjacent the edges of the substrate face and relatively small adjacent the center of the substrate face. By sizing each capture pad based on the maximum positional variation at the particular capture pad position, higher contact density is obtainable than with known uniform size capture pads. The variable size capture pads may also be used at one or more rows of capture pads located along one or more edges of the substrate, for electrical connection to an edge connector. For example, assuming a minimum shrinkage reference point at the center of the row, the capture pads are relatively large adjacent the ends of the row of capture pads and are relatively small adjacent the center of the row.

Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

Abstract: The fluxless bonding in a reducing atmosphere of integrated circuit contacts containing copper is enhanced using a layer of 200 to 1500 Angstrom thick palladium which inhibits copper oxide formation before fusion and reduces all oxides to promote wetting during fusion.

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

Abstract: The fluxless bonding in a reducing atmosphere of integrated circuit contacts containing copper is enhanced using a layer of 200 to 1500 Angstrom thick palladium which inhibits copper oxide formation before fusion and reduces all oxides to promote wetting during fusion.

Abstract: A heat resistant brazing alloy of a major amount of gold, a lesser amount of indium and a minor amount of tin. The alloy is particularly suited for use in bonding electrical components to chip carrying substrates which are to be reworked.

Abstract: The top surface metallurgy of LSI chip carriers is improved by multiple and phased interface of metal layers which enable such metallurgies to be suitable for joining by solder reflow and wire bonding techniques. The modifications result in separating the solder bonding metallurgy from the fan-out conductor metallurgy with an intermediate layer of a metal such as Cr or Ti which prevents the formation of intermetallic alloys which are mechanically weak or brittle and tend to fracture because of thermal fatigue stresses caused by thermal cycling during either multiple (up to 50) solder bonding reflow operations or operation of the circuit. The fan-out metallurgy conductors are preferably composed of Cr-Cu-Cr layers covered by at least one upper metal layer which is separated from the Cu of the conductor by means of a metal such as phased layers of Cr or Ti deposited before the other upper metal layer or layers. Solder ball bonding surfaces are composed of additional metal in the form of Au, Cu and Ni.

Abstract: A controlled geometric configuration of contact pads for securing solder mounds to an integrated circuit chip which reduces cracking of brittle passivating coatings in fabrication of components.

Abstract: Extraction of non-lead components (e.g. tin, indium, etc.) from solder joints with monocarboxylic acids of alkylated hydrophenanthrene nuclei to increase the lead content of the solder joints.