Patents by Inventor Nicholas Haehn
Nicholas Haehn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240078702Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.Type: ApplicationFiled: September 5, 2022Publication date: March 7, 2024Inventors: Yi LI, Hong Seung YEON, Nicholas HAEHN, Wei LI, Raquel DE SOUZA BORGES FERREIRA, Minglu LIU, Robin McREE, Yosuke KANAOKA, Gang DUAN, Arnab ROY
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Publication number: 20240079259Abstract: The present disclosure is directed to a system that uses a dual surface substrate carrier that includes a first transparent support with a first top surface and first bottom surface, a second transparent support with a second top surface and second bottom surface, and a reflective film positioned between and attached to the first transparent support and the second transparent support. The first transparent support has a first set of trenches configured in the first top surface that form a first set of ridges between the plurality of trenches and the second transparent support has a second set of trenches configured in the second top surface that form a second set of ridges between the plurality of trenches. The first transparent support is also configured with a first build surface and the second transparent support is also configured with a second build surface that are platforms for building package substrates.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Inventors: Jacob VEHONSKY, Onur OZKAN, Vinith BEJUGAM, Mao-Feng TSENG, Andrea NICOLAS, Nicholas HAEHN
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Publication number: 20240079530Abstract: Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Jacob VEHONSKY, Onur OZKAN, Vinith BEJUGAM, Mao-Feng TSENG, Nicholas HAEHN, Andrea NICOLAS FLORES, Ali LEHAF, Benjamin DUONG, Joshua STACEY
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Publication number: 20240070366Abstract: A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Nicholas HAEHN, Raquel DE SOUZA BORGES FERREIRA, Siddharth ALUR, Prakaram JOSHI, Dhanya ATHREYA, Yidnekachew MEKONNEN, Ali HARIRI, Andrea NICOLAS, Sri Chaitra Jyotsna CHAVALI, Kemal AYGUN
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Patent number: 11652036Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.Type: GrantFiled: April 2, 2018Date of Patent: May 16, 2023Inventors: Jeremy Ecton, Hiroki Tanaka, Kristof Kuwawi Darmawikarta, Oscar Ojeda, Arnab Roy, Nicholas Haehn
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Patent number: 11640929Abstract: An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.Type: GrantFiled: December 20, 2018Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Divya Mani, Nicholas Haehn
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Patent number: 11594463Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.Type: GrantFiled: October 11, 2018Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Nicholas Haehn
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Patent number: 11528811Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: GrantFiled: June 1, 2021Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Publication number: 20220102231Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled thereto. A dummy die structure extends to a bottom of a recess structure formed by a first package mold structure on the substrate. The dummy die structure comprises a polymer resin and a filler, or comprises a metal which has a low coefficient of thermal expansion (CTE). A second package mold structure, which extends to the recess structure, is adjacent to the first package mold structure and to an IC die. In another embodiment, a first CTE of the dummy die is less than a second CTE of one of the package mold structures, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the one of the package mold structures.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane
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Publication number: 20220102242Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
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Publication number: 20210289638Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Patent number: 11116084Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: GrantFiled: September 27, 2017Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Publication number: 20200236795Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.Type: ApplicationFiled: September 27, 2017Publication date: July 23, 2020Applicant: INTEL CORPORATIONInventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
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Publication number: 20200203256Abstract: An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: Nicholas Neal, Divya Mani, Nicholas Haehn
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Publication number: 20200118902Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.Type: ApplicationFiled: October 11, 2018Publication date: April 16, 2020Applicant: Intel CorporationInventors: Nicholas Neal, Nicholas Haehn
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Publication number: 20190304890Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Applicant: Intel CorporationInventors: Jeremy Ecton, Hiroki Tanaka, Kristof Kuwawi Darmawikarta, Oscar Ojeda, Arnab Roy, Nicholas Haehn