Abstract: Virtual processors are mappable to a number of physical processors. An interrupt distributor is responsible for distributing interrupt requests to a subset of the physical processors. An interface communicates with further interrupt distributors responsible for other physical processors. In response to an interrupt request to be handled by a target virtual processor, the interrupt distributor determines, based on cached virtual processor mapping information, whether to route the interrupt request to one of the subset of physical processors or to one of the further interrupt distributors. When a rejection response is received in response to an interrupt request routed to one of the further interrupt distributors, an update of the cached virtual processing mapping information is requested based on shared virtual processor mapping information, and a resent interrupt request is sent to a further interrupt distributor determined based on the shared virtual processor mapping information.

Abstract: An apparatus comprises an interrupt distributor to distribute virtual interrupts to one or more physical processors, each virtual interrupt to be handled by one of a plurality of virtual processors mappable to said one or more physical processors; and control circuitry to maintain virtual processor interrupt tracking information corresponding to a given virtual processor. The virtual processor interrupt tracking information includes a pending interrupt record tracking which types of virtual interrupts are pending for the given virtual processor, and separate from the pending interrupt record, a pending interrupt status indication indicating a pending interrupt status for the given virtual processor. The pending interrupt status indicates whether the number of pending virtual interrupts for the given virtual processor is zero.

Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.

Abstract: An electrical device having a bus side and a load side is provided. The electrical device includes a plurality of conductive line terminals disposed on the bus side of said electrical device, and a plurality of electrical connectors. Each electrical connector of the plurality of electrical connectors includes a first end coupled to a respective line terminal of the plurality of line terminals, a second end distal from the first end, and a connector clip disposed at the second end. Each connector clip is configured to engage a bus bar to electrically couple the electrical device to the bus bar, and includes a first contact segment and a second contact segment spaced apart from the first contact segment. The first and second contact segments are configured to deflect towards one another from a relaxed position to a depressed position when inserted into a connector channel defined by the bus bar.

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing instructions relating to an active virtual processor in a plurality of virtual processors. Exception control circuitry receives an external exception associated with a target virtual processor in the plurality of virtual processors and when the target virtual processor is other than the active virtual processor, it issues a doorbell exception to cause a scheduling operation to schedule the target virtual processor to be the active virtual processor. Storage circuitry stores an indication of a set of masked virtual processors and the scheduling operation is adapted to disregard doorbell exceptions in respect of the set of masked virtual processors.

Abstract: An electrical device having a bus side and a load side is provided. The electrical device includes a plurality of conductive line terminals disposed on the bus side of said electrical device, and a plurality of electrical connectors. Each electrical connector of the plurality of electrical connectors includes a first end coupled to a respective line terminal of the plurality of line terminals, a second end distal from the first end, and a connector clip disposed at the second end. Each connector clip is configured to engage a bus bar to electrically couple the electrical device to the bus bar, and includes a first contact segment and a second contact segment spaced apart from the first contact segment. The first and second contact segments are configured to deflect towards one another from a relaxed position to a depressed position when inserted into a connector channel defined by the bus bar.

Abstract: An electrical device having a bus side and a load side is provided. The electrical device includes a plurality of conductive line terminals disposed on the bus side of said electrical device, and a plurality of electrical connectors. Each electrical connector of the plurality of electrical connectors includes a first end coupled to a respective line terminal of the plurality of line terminals, a second end distal from the first end, and a connector clip disposed at the second end. Each connector clip is configured to engage a bus bar to electrically couple the electrical device to the bus bar, and includes a first contact segment and a second contact segment spaced apart from the first contact segment. The first and second contact segments are configured to deflect towards one another from a relaxed position to a depressed position when inserted into a connector channel defined by the bus bar.

Abstract: An electrical device having a bus side and a load side is provided. The electrical device includes a plurality of conductive line terminals disposed on the bus side of said electrical device, and a plurality of electrical connectors. Each electrical connector of the plurality of electrical connectors includes a first end coupled to a respective line terminal of the plurality of line terminals, a second end distal from the first end, and a connector clip disposed at the second end. Each connector clip is configured to engage a bus bar to electrically couple the electrical device to the bus bar, and includes a first contact segment and a second contact segment spaced apart from the first contact segment. The first and second contact segments are configured to deflect towards one another from a relaxed position to a depressed position when inserted into a connector channel defined by the bus bar.

Abstract: An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.

Abstract: This invention relates to intermediates useful in the preparation of opiate alkaloids, particularly morphinane compounds. The invention also relates to processes for preparing such intermediates and to processes which utilise such intermediates in the synthesis of morphinane compounds.

Abstract: This invention relates to intermediates useful in the preparation of opiate alkaloids, particularly morphinane compounds. The invention also relates to processes for preparing such intermediates and to processes which utilise such intermediates in the synthesis of morphinane compounds.

Abstract: This invention relates to intermediates useful in the preparation of opiate alkaloids, particularly morphinane compounds. The invention also relates to processes for preparing such intermediates and to processes which utilise such intermediates in the synthesis of morphinane compounds.

Abstract: This invention relates to intermediates useful in the preparation of opiate alkaloids, particularly morphinane compounds. The invention also relates to processes for preparing such intermediates and to processes which utilise such intermediates in the synthesis of morphinane compounds.