Patents by Inventor Nicholas Heath

Nicholas Heath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230031446
    Abstract: The present invention provides methods and compositions for detecting genomic sequences of interest in living cells. In particular, the present disclosure provides a split-enzyme system that works with guide RNAs and RNA-guided nucleases to produce detectable luminescent signals exclusively in the presence of targeted genomic sequences.
    Type: Application
    Filed: November 23, 2020
    Publication date: February 2, 2023
    Inventors: David J. Segal, Nicholas Heath, Henriette O'Geen, Jacob Corn
  • Patent number: 10076062
    Abstract: A amplifier with improved space efficiency includes a housing that dissipates heat having an upper wall and two side walls and having an interior with upper and lower portions. The amplifier further includes an upper circuit board in the upper portion and a lower circuit board in a lower portion. The amplifier further includes a connector that electrically connects the upper and lower circuit boards.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: September 11, 2018
    Inventor: Nicholas Heath Wright
  • Publication number: 20150349714
    Abstract: A amplifier with improved space efficiency includes a housing that dissipates heat having an upper wall and two side walls and having an interior with upper and lower portions. The amplifier further includes an upper circuit board in the upper portion and a lower circuit board in a lower portion. The amplifier further includes a connector that electrically connects the upper and lower circuit boards.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 3, 2015
    Inventor: Nicholas Heath Wright
  • Patent number: 8847785
    Abstract: The teachings herein disclose a method and apparatus for preventing excessive battery passivation in an electronic meter-reading module. The module operates in a low-power state most of the time. The low-power state is interrupted at defined transmit times, wherein the module temporarily turns on or otherwise activates an included communication transmitter, for the transmission of data to a remote node reachable through a wireless communication network. Because of its low current draw during the times between data transmissions, the module's battery is vulnerable to passivation layer buildup. Advantageously, however, the module is configured to perform dummy activations of its transmitter at times other than the defined transmit times, e.g., in the intervals between data transmissions. These dummy activations are not for data transmission, but rather are temporary activations of the relatively high-power transmitter, for reducing passivation layer buildup on the battery in advance of a next data transmission.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: September 30, 2014
    Assignee: Sensus USA Inc.
    Inventor: Nicholas Heath
  • Publication number: 20120280830
    Abstract: The teachings herein disclose a method and apparatus for preventing excessive battery passivation in an electronic meter-reading module. The module operates in a low-power state most of the time. The low-power state is interrupted at defined transmit times, wherein the module temporarily turns on or otherwise activates an included communication transmitter, for the transmission of data to a remote node reachable through a wireless communication network. Because of its low current draw during the times between data transmissions, the module's battery is vulnerable to passivation layer buildup. Advantageously, however, the module is configured to perform dummy activations of its transmitter at times other than the defined transmit times, e.g., in the intervals between data transmissions. These dummy activations are not for data transmission, but rather are temporary activations of the relatively high-power transmitter, for reducing passivation layer buildup on the battery in advance of a next data transmission.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Applicant: SENSUS USA INC.
    Inventor: Nicholas Heath
  • Patent number: 7843753
    Abstract: An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: November 30, 2010
    Assignee: Qimonda AG
    Inventors: Peter Mayer, Nicholas Heath, Rom-Shen Kao, Jason Parrish
  • Patent number: 7746098
    Abstract: Embodiments of the invention are generally related to systems comprising devices connected by a bus. A device in the system may include termination control logic capable of detecting changes in the system clock frequency. Upon detecting a clock frequency, the termination control logic may determine whether the clock frequency is greater than a threshold frequency. If so, the termination control logic may enable bus termination. However, if the new clock frequency is lower than the threshold frequency, bus termination may be disabled, thereby conserving power.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: June 29, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Nicholas Heath, Peter Mayer
  • Patent number: 7715264
    Abstract: In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation which causes insubstantial signal reflections at the I/O signals. The control circuitry re-enables the termination circuitry prior to the electronic device performing a relatively high frequency operation after completion of the low frequency operation, the high frequency operation causing substantial signal reflections at the I/O signals. The electronic device is a memory device in one embodiment. This way, the termination circuitry may be disabled during at least a portion of a refresh operation performed by the memory device and re-enabled prior to the memory device resuming normal operation (i.e., reads and writes) after completion of the refresh operation.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: May 11, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Peter Meyer, Nicholas Heath
  • Publication number: 20090316511
    Abstract: In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation which causes insubstantial signal reflections at the I/O signals. The control circuitry re-enables the termination circuitry prior to the electronic device performing a relatively high frequency operation after completion of the low frequency operation, the high frequency operation causing substantial signal reflections at the I/O signals. The electronic device is a memory device in one embodiment. This way, the termination circuitry may be disabled during at least a portion of a refresh operation performed by the memory device and re-enabled prior to the memory device resuming normal operation (i.e., reads and writes) after completion of the refresh operation.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Applicant: Qimonda North America Corp.
    Inventors: Peter Mayer, Nicholas Heath
  • Publication number: 20090238020
    Abstract: An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Inventors: Peter Mayer, Nicholas Heath, Rom-Shen Kao, Jason Parrish
  • Publication number: 20090224796
    Abstract: Embodiments of the invention are generally related to systems comprising devices connected by a bus. A device in the system may include termination control logic capable of detecting changes in the system clock frequency. Upon detecting a clock frequency, the termination control logic may determine whether the clock frequency is greater than a threshold frequency. If so, the termination control logic may enable bus termination. However, if the new clock frequency is lower than the threshold frequency, bus termination may be disabled, thereby conserving power.
    Type: Application
    Filed: March 10, 2008
    Publication date: September 10, 2009
    Inventors: NICHOLAS HEATH, Peter MAYER
  • Patent number: D756973
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 24, 2016
    Inventor: Nicholas Heath Wright