Patents by Inventor Nicholas J. Foskett
Nicholas J. Foskett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7809782Abstract: A method for selecting a set of parameters from a parameter space of a contemplated implementation of a pipelined processor for configuring the processor to generate an output word in response to each of a set of input words. The method includes determining a mapping between each set of parameters in the parameter space and the area of an integrated circuit implementation of the processor, and searching the parameter space to select a preferred set of the parameters that minimizes the area of the integrated circuit implementation subject to the constraints that each of the input word and the output word has specified format and that the preferred set of the parameters results in no more than a specified maximum error between the function of each of the input values and the approximation of the function of said each of the input values.Type: GrantFiled: September 6, 2006Date of Patent: October 5, 2010Assignee: NVIDIA CorporationInventors: Nicholas J. Foskett, Robert J. Prevett, Jr., Sean Treichler
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Patent number: 7117238Abstract: A pipelined circuit configured to generate a Taylor's series approximation at least one function, preferably at least one of the reciprocal and the reciprocal square root, of an input value. The circuit is preloaded with or configured to generate a predetermined set of Taylor's series coefficients for each segment of the input value range. Other aspects of the invention are methods for determining preferred parameters for elements of such a circuit, a circuit designed in accordance with such a method, and a system (e.g., a pipelined graphics processor) for and method of pipelined graphics data processing using any embodiment of the circuit. The preferred parameters are determined by minimizing the circuit's size subject to constraints on input and output value format and output accuracy, assuming a specific function to be approximated and a specific degree for the approximation but allowing variation of parameters such as coefficient width and number of input value range segments.Type: GrantFiled: September 19, 2002Date of Patent: October 3, 2006Assignee: NVIDIA CorporationInventors: Nicholas J. Foskett, Robert J. Prevett, Jr., Sean Treichler
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Patent number: 7064763Abstract: A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module positioned on a single semiconductor platform for transforming graphics data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data.Type: GrantFiled: June 28, 2002Date of Patent: June 20, 2006Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 7050055Abstract: A graphics pipeline system and associated method are provided for graphics processing. Such system includes a transform module adapted for receiving graphics data. The transform module serves to transform the graphics data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. During use, the graphics pipeline system is capable of carrying out a fog and blending operation.Type: GrantFiled: June 28, 2002Date of Patent: May 23, 2006Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 7034829Abstract: A graphics pipeline system with an integrated masking operation is provided. Included is a transform module adapted for being coupled to a buffer to receive graphics data therefrom. Such transform module is positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space. Also included is a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module. The lighting modules serves for performing lighting operations on the graphics data received from the transform module. In use, a masking operation is further performed on the single semiconductor platform.Type: GrantFiled: September 20, 2001Date of Patent: April 25, 2006Assignee: Nvidia CorporationInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 7002577Abstract: A graphics pipeline system and associated method are provided with an integrated clipping operation. First included is a transform module positioned on a single semiconductor platform for transforming graphics data from a first space to a second space. Also provided is a lighting module positioned on the same single semiconductor platform as the transform module. The lighting module is adapted for performing lighting operations on the graphics data. A clipping operation is also performed utilizing the single semiconductor platform.Type: GrantFiled: June 28, 2002Date of Patent: February 21, 2006Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 6992667Abstract: A graphics hardware system and method are provided for graphics processing. Such system includes a transform module positioned on a single semiconductor platform for transforming graphics data. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data. As an option, the graphics hardware system may further be equipped with skinning, swizzling and masking capabilities.Type: GrantFiled: March 31, 2003Date of Patent: January 31, 2006Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 6957298Abstract: A memory controller system is provided including a plurality of memory controller subsystems each coupled between memory and one of a plurality of computer components. Each memory controller subsystem includes at least one queue for managing pages in the memory. In use, each memory controller subsystem is capable of being loaded from the associated computer component independent of the state of the memory. Since high bandwidth and low latency are conflicting requirements in high performance memory systems, the present invention separates references from various computer components into multiple command streams. Each stream thus can hide activate bank preparation commands within its own stream for maximum bandwidth. A page context switch technique may be employed that allows instantaneous switching from one look ahead stream to another to allow low latency and high bandwidth while preserving maximum bank state from the previous stream.Type: GrantFiled: September 8, 2003Date of Patent: October 18, 2005Assignee: NVIDIA CorporationInventors: James M. Van Dyke, Nicholas J. Foskett, Brad Simeral, Sean Treichler
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Patent number: 6765575Abstract: Clip-less rasterization is provided by a plurality of operations. First, a primitive is received that is defined by a plurality of vertices. Each of such vertices includes a W-value. Thereafter, an area is identified based on the W-values. Such area is representative of a portion of a display to be drawn corresponding to the primitive.Type: GrantFiled: December 6, 1999Date of Patent: July 20, 2004Assignee: Nvidia CorporationInventors: Douglas A. Voorhies, Nicholas J. Foskett, Matthew N. Papakipos
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Patent number: 6650331Abstract: A graphics pipeline system is provided with an integrated scissor operation. First provided is a transform module adapted for being coupled to a buffer to receive graphics data therefrom. Such transform module is positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space. Associated therewith is a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the graphics data received from the transform module. A scissor operation is performed on the same single semiconductor platform as the transform module and the lighting module.Type: GrantFiled: September 20, 2001Date of Patent: November 18, 2003Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 6650325Abstract: A method, apparatus and article of manufacture are provided for performing rasterization using alternating sense point traversal. Upon receipt of a primitive, i.e. a triangle, a plurality of points are positioned on or near the primitive. Such points define an enclosed convex region and may be located at corners of the convex region. In operation, the points and convex region are moved in an alternating manner for the purpose of identifying an area in the primitive for rendering pixels therein. In particular, the points are moved in a boustrophedonic manner.Type: GrantFiled: December 6, 1999Date of Patent: November 18, 2003Assignee: NVIDIA CorporationInventors: Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 6647456Abstract: At memory controller system is provided including a plurality of memory controller subsystems each coupled between memory and one of a plurality of computer components. Each memory controller subsystem includes at least one queue for managing pages in the memory. In use, each memory controller subsystem is capable of being loaded from the associated computer component independent of the state of the memory. Since high bandwidth and low latency are conflicting requirements in high performance memory systems, the present invention separates references from various computer components into multiple command streams. Each stream thus can hide precharge and activate bank preparation commands within its own stream for maximum bandwidth.Type: GrantFiled: February 23, 2001Date of Patent: November 11, 2003Assignee: NVIDIA CorporationInventors: James M. Van Dyke, Nicholas J. Foskett, Brad Simeral, Sean Treichler
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Publication number: 20030189565Abstract: A graphics hardware system and method are provided for graphics processing. Such system includes a transform module positioned on a single semiconductor platform for transforming graphics data. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data. As an option, the graphics hardware system may further be equipped with skinning, swizzling and masking capabilities.Type: ApplicationFiled: March 31, 2003Publication date: October 9, 2003Applicant: NVIDIA CORPORATIONInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Publication number: 20030112245Abstract: A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module positioned on a single semiconductor platform for transforming graphics data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data.Type: ApplicationFiled: June 28, 2002Publication date: June 19, 2003Applicant: nVIDIA CORPORATIONInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 6577309Abstract: A graphics pipeline system is provided with a transform module positioned on a single semiconductor platform for transforming graphics data. Also included is a lighting module positioned on the same single semiconductor platform as the transform module for lighting the graphics data. In use, various operations may be performed utilizing the single semiconductor platform such as rendering, fog operations, blending, coloring operations, etc.Type: GrantFiled: September 20, 2001Date of Patent: June 10, 2003Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Publication number: 20030103050Abstract: A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for being coupled to a vertex attribute buffer for receiving vertex data. The transform module serves to transform the vertex data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module.Type: ApplicationFiled: September 20, 2001Publication date: June 5, 2003Inventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 6504542Abstract: A method, apparatus and article of manufacture are provided for performing area rasterization using sense points. Upon receipt of a primitive, e.g. a triangle, line equation coefficients of line equations are determined for lines that define the primitive. Thereafter, a plurality of points is positioned on or near the primitive. Such points define an enclosed convex region. Next, the line equations are evaluated at the points. During operation, the points and convex region are moved based on the evaluation of the line equations for the purpose of identifying an area in the primitive for rendering pixels therein.Type: GrantFiled: December 6, 1999Date of Patent: January 7, 2003Assignee: Nvidia CorporationInventors: Douglas A. Voorhies, Nicholas J. Foskett
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Publication number: 20020196259Abstract: A graphics pipeline system and associated method are provided for graphics processing. Such system includes a transform module adapted for receiving graphics data. The transform module serves to transform the graphics data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. During use, the graphics pipeline system is capable of carrying out a fog and blending operation.Type: ApplicationFiled: June 28, 2002Publication date: December 26, 2002Applicant: nVIDIA CORPORATIONInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Publication number: 20020180740Abstract: A graphics pipeline system and associated method are provided with an integrated clipping operation. First included is a transform module positioned on a single semiconductor platform for transforming graphics data from a first space to a second space. Also provided is a lighting module positioned on the same single semiconductor platform as the transform module. The lighting module is adapted for performing lighting operations on the graphics data. A clipping operation is also performed utilizing the single semiconductor platform.Type: ApplicationFiled: June 28, 2002Publication date: December 5, 2002Applicant: nVIDIA CORPORATIONInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett
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Patent number: 6462737Abstract: A graphics pipeline system is provided with an integrated clipping operation. First included is a transform module adapted for being coupled to a buffer to receive graphics data therefrom. Such transform module is positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space. Also provided is a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module. The lighting module is adapted for performing lighting operations on the graphics data received from the transform module. A range clamp inversion function and a clipping operation are performed on the same single semiconductor platform as the transform module and the lighting module.Type: GrantFiled: September 20, 2001Date of Patent: October 8, 2002Assignee: Nvidia CorporationInventors: John Erik Lindholm, Simon Moy, Kevin Dawallu, Mingjian Yang, John Montrym, David B. Kirk, Paolo E. Sabella, Matthew N. Papakipos, Douglas A. Voorhies, Nicholas J. Foskett