Abstract: A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.

Abstract: Wireless devices are easily configured with logical network and security settings. Configuration commands are received at master and slave wireless devices. The devices switch to predetermined logical network and security settings to allow communication between the master and slave devices. The master device selects a logical network and/or security setting and sends the setting(s) to the slave device. Both devices then switch to the selected setting(s) and use the setting(s) for future communications.

Abstract: A system and method for implementing high speed input and output protocols in software using hard real time threads. The processor provides both high speed and deterministic performance. The hard real time threads execute enough instructions per clock cycle of the input and output protocol to regularly transfer data.

Abstract: A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.

Abstract: An apparatus and method to provide a data processing system with reduced average power consumption while maintaining fast interrupt handling, and/or selectively change clock frequency for accessing memory with various access speeds. In a first embodiment, the invention provides a method to deterministically change a clock frequency between a first clock frequency and a second clock frequency in a data processing system to process operations upon the occurrence of a condition. In a second embodiment, the invention provides a method to change the clock frequency of a data processing system to process operations upon the occurrence of a condition. In a third embodiment, the invention provides a clock divider circuit to produce a core clock signal. In a fourth embodiment, the invention provides a data processing system with a deterministically variable processor clock.

Abstract: A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.

Abstract: A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.