Abstract: A digital video encoder (16) receives a reference clock signal (REF_CLK27) for determining both a short term and a long term phase correction factor. A pulse detector (46) determines a number of sample clock (CLK324) time periods between the reference clock signal (REF_CLK27) and a clock signal (CLK27) that is derived from the data received by the digital video encoder (16). A phase increment generator (56) supplies an accumulator circuit (58) with a long term phase increment value based on the number of sample clocks and a TV_standard signal. A counter (60) and a phase look-up table (62) supply a short term increment value. The combined short term and long term increment values provide phase and frequency accuracy for the video subcarrier signal.

Abstract: A BIST circuit that can be placed in a halt mode has been provided. During halt, the operation of the BIST circuit is stopped when an error has been detected thereby allowing for faster location of the error. The BIST circuit also includes a memory access mode which allows for independent read or write access to a predetermined address of a storage device under test.

Abstract: A built-in self test (BIST) circuit verifies the operation of a circuit under test in an integrated circuit. The BIST generates a series of test vectors with linear feedback shift register (LFSR) and applies the test vectors to the circuit under test. The output signal from the circuit under test in response to the test vectors is routed back and accumulating in a predetermined manner in the LFSR for providing a test signature. Thus, the same components in the LFSR generating the test vector also perform the accumulation of the test signature. The accumulating test signature may be used as a subsequent test vector.