Abstract: Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous digital signal, e.g., a DS3 signal, from a received synchronous digital signal, e.g., a SONET STS-1 signal. The improved jitter performance results from the use of a unique dynamic bit leaking arrangement in conjunction with a digital phase locked loop and desynchronizing elastic store. An optimum bit leak interval is obtained by controllably leaking a greater number of shorter interval STS-1 bits than the number of received pointer adjustment bits or, alternatively, leaking a fewer number of longer interval bits than the net number of received pointer adjustment bits. Additionally, the affect of random pointer adjustments and the superposition of randomly received pointer adjustments on a periodic sequence of received pointer adjustments is minimized by employing a "static" queue of pointer adjustment bits to be leaked.

Abstract: Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous digital signal, e.g., a DS3 signal, from a received synchronous digital signal, e.g., a SONET STS-1 signal. The improved jitter performance results from the use of a unique dynamic bit leaking arrangement in conjunction with a digital phase locked loop and desynchronizing elastic store. An optimum bit leak interval is obtained by controllably leaking a greater number of shorter interval STS-1 bits than the number of received pointer adjustment bits. Additionally, the affect of random pointer adjustments and the superposition of randomly received pointer adjustments on a periodic sequence of received pointer adjustments is minimized by employing a "static" queue of pointer adjustment bits to be leaked. The queue is dynamically maintained at its "static" count so that there are always bits in the queue to be leaked at the desired optimum bit leak interval even in the presence of randomly received pointer adjustments.

Abstract: A digital phase locked loop is employed to realize an output clock signal from a reference signal having a frequency which is not an integer multiple of the output clock signal frequency. This is realized by employing a programmable divider for dividing the reference signal which is dynamically controlled by a controllably variable base divisor. The base divisor control is responsive to the reference signal and to a phase error signal. The base divisor is generated to obtain a desired fractional division of the reference signal frequency and in a manner to minimize the amplitude of any resulting "high" frequency jitter in the output clock signal from the loop.