Patents by Inventor Nicholas J. Richardson
Nicholas J. Richardson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11334413Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.Type: GrantFiled: January 27, 2020Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
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Patent number: 10846175Abstract: A product code decoder to implement a method of bit correction in a codeword buffer to support error correcting code (ECC). The method loads a location entry from a correction queue, where the location entry includes a data word address and bit location information. The method performs a fast path data word address comparison to determine whether data from the data word address is being processed by a previous entry from the correction queue. The method further combines a correction of the data at the data word address specified by the location entry with a correction of a copy of the data being processed based on a previous location entry, in response to a fast path data word address comparison match, and stores the combined data in the codeword buffer.Type: GrantFiled: April 10, 2018Date of Patent: November 24, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Sivagnanam Parthasarathy, Nicholas J. Richardson, Patrick R. Khayat, Shantilal Doru
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Publication number: 20200159616Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.Type: ApplicationFiled: January 27, 2020Publication date: May 21, 2020Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
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Patent number: 10628256Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.Type: GrantFiled: January 10, 2019Date of Patent: April 21, 2020Assignee: Micron Technology, Inc.Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
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Patent number: 10572338Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.Type: GrantFiled: August 6, 2018Date of Patent: February 25, 2020Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
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Publication number: 20190310912Abstract: A product code decoder to implement a method of bit correction in a codeword buffer to support error correcting code (ECC). The method loads a location entry from a correction queue, where the location entry includes a data word address and bit location information. The method performs a fast path data word address comparison to determine whether data from the data word address is being processed by a previous entry from the correction queue. The method further combines a correction of the data at the data word address specified by the location entry with a correction of a copy of the data being processed based on a previous location entry, in response to a fast path data word address comparison match, and stores the combined data in the codeword buffer.Type: ApplicationFiled: April 10, 2018Publication date: October 10, 2019Inventors: Sivagnanam Parthasarathy, Nicholas J. Richardson, Patrick R. Khayat, Shantilal Doru
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Publication number: 20190312600Abstract: A method and system for implementing error correcting code using a product code decoder. The method and system receive a product code, wherein the product code is a matrix of row and column component codes, generate a plurality of row syndromes column syndromes from the received product code, store the plurality of row syndromes in a row syndrome queue, store the plurality of column syndromes in a column syndrome queue, the column and row syndrome queue to support the plurality of modes of operation corresponding to the plurality of phases of decoding the product code, correct the plurality of row syndromes and columns syndromes in the row and column syndrome queues based on errors detected in respective row and column syndromes and errors detecting in overlapping syndromes, and correct the product code in a codeword buffer at locations corresponding to corrections in the plurality of row syndromes and the plurality of column syndromes.Type: ApplicationFiled: April 10, 2018Publication date: October 10, 2019Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Shantilal Doru, Nicholas J. Richardson
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Patent number: 10439648Abstract: A method and system for implementing error correcting code using a product code decoder. The method and system receive a product code, wherein the product code is a matrix of row and column component codes, generate a plurality of row syndromes column syndromes from the received product code, store the plurality of row syndromes in a row syndrome queue, store the plurality of column syndromes in a column syndrome queue, the column and row syndrome queue to support the plurality of modes of operation corresponding to the plurality of phases of decoding the product code, correct the plurality of row syndromes and columns syndromes in the row and column syndrome queues based on errors detected in respective row and column syndromes and errors detecting in overlapping syndromes, and correct the product code in a codeword buffer at locations corresponding to corrections in the plurality of row syndromes and the plurality of column syndromes.Type: GrantFiled: April 10, 2018Date of Patent: October 8, 2019Assignee: MICRON TECHNOLOGY, INC.Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Shantilal Doru, Nicholas J. Richardson
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Patent number: 10326479Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.Type: GrantFiled: July 11, 2016Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy, Nicholas J. Richardson
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Publication number: 20190146866Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.Type: ApplicationFiled: January 10, 2019Publication date: May 16, 2019Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
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Patent number: 10191804Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.Type: GrantFiled: May 17, 2016Date of Patent: January 29, 2019Assignee: Micron Technology, Inc.Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
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Publication number: 20180341546Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.Type: ApplicationFiled: August 6, 2018Publication date: November 29, 2018Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
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Patent number: 10061643Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.Type: GrantFiled: December 16, 2016Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
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Publication number: 20180013451Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.Type: ApplicationFiled: July 11, 2016Publication date: January 11, 2018Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy, Nicholas J. Richardson
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Publication number: 20170097859Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.Type: ApplicationFiled: December 16, 2016Publication date: April 6, 2017Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
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Patent number: 9612903Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.Type: GrantFiled: October 11, 2012Date of Patent: April 4, 2017Assignee: Micron Technology, Inc.Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
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Patent number: 9558064Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.Type: GrantFiled: January 28, 2015Date of Patent: January 31, 2017Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
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Publication number: 20160259686Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.Type: ApplicationFiled: May 17, 2016Publication date: September 8, 2016Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
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Publication number: 20160218740Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.Type: ApplicationFiled: January 28, 2015Publication date: July 28, 2016Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
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Publication number: 20140108883Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.Type: ApplicationFiled: October 11, 2012Publication date: April 17, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson