Patents by Inventor Nicholas J. Richardson

Nicholas J. Richardson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200159616
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Patent number: 10628256
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 10595580
    Abstract: A helmet mounted protective shroud apparatus for use with respirators includes a shroud mating component adapted to surround a respirator and a shroud component connected to the shroud mating component. The shroud component includes a fabric component having an edge, a plurality of connection mechanisms connected to the fabric component, and a flap component configured to cover a top of the fabric component, wherein the shroud component is adapted to cover a helmet and surround a wearer's head and neck. The present invention allows a chemical-biological protective hood/shroud assembly to be integrated for use with a helmet and respirator.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 24, 2020
    Assignee: The United States of America as Represented by the Secretary of the Army
    Inventors: Douglas E. Wilke, Daniel J Barker, Corey M Grove, Kristin J Birdsall, Michael A Lorenz, Thomas A Pettenski, Aaron W Richardson, Nicholas E Knebel
  • Patent number: 10572338
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Publication number: 20190310912
    Abstract: A product code decoder to implement a method of bit correction in a codeword buffer to support error correcting code (ECC). The method loads a location entry from a correction queue, where the location entry includes a data word address and bit location information. The method performs a fast path data word address comparison to determine whether data from the data word address is being processed by a previous entry from the correction queue. The method further combines a correction of the data at the data word address specified by the location entry with a correction of a copy of the data being processed based on a previous location entry, in response to a fast path data word address comparison match, and stores the combined data in the codeword buffer.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 10, 2019
    Inventors: Sivagnanam Parthasarathy, Nicholas J. Richardson, Patrick R. Khayat, Shantilal Doru
  • Publication number: 20190312600
    Abstract: A method and system for implementing error correcting code using a product code decoder. The method and system receive a product code, wherein the product code is a matrix of row and column component codes, generate a plurality of row syndromes column syndromes from the received product code, store the plurality of row syndromes in a row syndrome queue, store the plurality of column syndromes in a column syndrome queue, the column and row syndrome queue to support the plurality of modes of operation corresponding to the plurality of phases of decoding the product code, correct the plurality of row syndromes and columns syndromes in the row and column syndrome queues based on errors detected in respective row and column syndromes and errors detecting in overlapping syndromes, and correct the product code in a codeword buffer at locations corresponding to corrections in the plurality of row syndromes and the plurality of column syndromes.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 10, 2019
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Shantilal Doru, Nicholas J. Richardson
  • Patent number: 10439648
    Abstract: A method and system for implementing error correcting code using a product code decoder. The method and system receive a product code, wherein the product code is a matrix of row and column component codes, generate a plurality of row syndromes column syndromes from the received product code, store the plurality of row syndromes in a row syndrome queue, store the plurality of column syndromes in a column syndrome queue, the column and row syndrome queue to support the plurality of modes of operation corresponding to the plurality of phases of decoding the product code, correct the plurality of row syndromes and columns syndromes in the row and column syndrome queues based on errors detected in respective row and column syndromes and errors detecting in overlapping syndromes, and correct the product code in a codeword buffer at locations corresponding to corrections in the plurality of row syndromes and the plurality of column syndromes.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 8, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Shantilal Doru, Nicholas J. Richardson
  • Patent number: 10326479
    Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy, Nicholas J. Richardson
  • Publication number: 20190146866
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 16, 2019
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 10191804
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Publication number: 20180341546
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Application
    Filed: August 6, 2018
    Publication date: November 29, 2018
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Patent number: 10061643
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Publication number: 20180013451
    Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.
    Type: Application
    Filed: July 11, 2016
    Publication date: January 11, 2018
    Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy, Nicholas J. Richardson
  • Publication number: 20170097859
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Application
    Filed: December 16, 2016
    Publication date: April 6, 2017
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Patent number: 9612903
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 9558064
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: January 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Publication number: 20160259686
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Publication number: 20160218740
    Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
    Type: Application
    Filed: January 28, 2015
    Publication date: July 28, 2016
    Inventors: Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat, Nicholas J. Richardson
  • Publication number: 20140108883
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 8055973
    Abstract: An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: November 8, 2011
    Assignee: STMicroelectronics, Inc.
    Inventors: Shayan Srinivasa Garani, Nicholas J. Richardson, Xinde Hu, Sivagnanam Parthasarathy