Patents by Inventor Nicholas J. Salatino

Nicholas J. Salatino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8129258
    Abstract: A method for dicing a semiconductor wafer, including: cutting a reference slot in a back main surface of the wafer; cutting a back slot in the back main surface, the back slot positioned with respect to the reference slot; determining a desired location for a chip edge with respect to the reference slot; and applying radiant energy in a path such that a series of reformed regions are formed within the wafer along the path. A crystalline structure of the wafer is modified in the series of reformed regions and an alignment of an edge of the laser is with respect to the desired location for the chip edge and in alignment with the back slot. The method includes separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Xerox Corporation
    Inventors: Paul A. Hosier, Nicholas J. Salatino
  • Publication number: 20110147898
    Abstract: A method for dicing a semiconductor wafer, including: cutting a reference slot in a back main surface of the wafer; cutting a back slot in the back main surface, the back slot positioned with respect to the reference slot; determining a desired location for a chip edge with respect to the reference slot; and applying radiant energy in a path such that a series of reformed regions are formed within the wafer along the path. A crystalline structure of the wafer is modified in the series of reformed regions and an alignment of an edge of the laser is with respect to the desired location for the chip edge and in alignment with the back slot. The method includes separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: XEROX CORPORATION
    Inventors: PAUL A. HOSIER, NICHOLAS J. SALATINO
  • Patent number: 6955989
    Abstract: The present disclosure relates that by modifying chip die dicing methodology to a U-groove profile from a V-groove profile by modifying the second etch step to be a dry etch instead of a wet etch results in a direct cost savings by eliminating a more expensive process step, as well as the need for stripping the developed photoresist layer. Furthermore, going to a U-groove profile accomplishes additional indirect and greater cost savings resulting from increased process throughput, improved yield, and reduced metal layer defects.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: October 18, 2005
    Assignee: Xerox Corporation
    Inventors: Alain E. Perregaux, Paul A. Hosier, Josef E. Jedlicka, Nicholas J. Salatino, Jagdish C. Tandon
  • Publication number: 20030194864
    Abstract: The present disclosure relates that by modifying chip die dicing methodology to a U-groove profile from a V-groove profile by modifying the second etch step to be a dry etch instead of a wet etch results in a direct cost savings by eliminating a more expensive process step, as well as the need for stripping the developed photoresist layer. Furthermore, going to a U-groove profile accomplishes additional indirect and greater cost savings resulting from increased process throughput, improved yield, and reduced metal layer defects.
    Type: Application
    Filed: November 30, 2001
    Publication date: October 16, 2003
    Applicant: Xerox Corporation.
    Inventors: Alain E. Perregaux, Paul A. Hosier, Josef E. Jedlicka, Nicholas J. Salatino, Jagdish C. Tandon
  • Patent number: 6291317
    Abstract: A method for dicing small devices including MEMS, ink jet printheads, lasers etc. The method comprises making a first pass cut into a substrate with a blade of narrow kerf and having long wear characteristics. This first pass cut is then followed with a polishing blade of wider kerf having desirable smooth cutting qualities.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: September 18, 2001
    Assignee: Xerox Corporation
    Inventors: Nicholas J. Salatino, John C. Ackerman