Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx 164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI Interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.

Abstract: An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.

Abstract: An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a red Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.

Abstract: An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: A method for building a compilable static RAM (SRAM). A central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a databus interface. A memory block macro (35) is built which includes a block of memory, precharge circuits, multiplexers, read/write multiplexers, and sense amplifiers. If multiple memory blocks are used a block deselect circuit (39) and row/block decoders (38) must be added to the memory block macro (35). A row and block deselection process is used in the SRAM architecture to simplify compilability and enhance speed.

Abstract: A data analyzer for use in BIST circuitry has been provided. The data analyzer allows both comparison analysis and signature analysis to be performed on a circuit response data stream. The data analyzer includes a plurality of data registers which are serially-coupled and where each data register is capable of performing comparison analysis and signature analysis on one data bit of the circuit response data stream. This allows the circuit under test can be completely and thoroughly tested for faults.

Abstract: A self-test that is variable to test an SRAM that is embedded on a semiconductor die is achieved. The self-test is performed by a modular self-test circuitry that can be varied to permit generating addresses, and data patterns for various SRAM architectures and sizes. An address block develops addresses which define a test location or test word within the SRAM. The address block also develops a time delay which is used during a data retention test. A data block develops test patterns that are written into SRAM test locations. The data block also analyzes data read from SRAM test locations or test words. Both the address block and the data block are formed by combining a number of individual address or data cells, thereby providing addresses and data patterns for a variety of different SRAM configurations. A control block operates the address block, the data block, and the SRAM to perform two memory tests.