Abstract: The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and has situated upon the dielectric region a layer of recrystallized silicon as a second active region. A gate electrode overlies both active regions and serves as a mask to form in such respective regions self-aligned channels. The concentric placement of the active substrate monocrystalline silicon region, and inner perimeter of dielectric, and a further inner active region of recrystallized silicon situated over a dielectric region, facilitates recrystallization from seed of monocrystalline silicon irrespective of the direction of translation taken by the energy beam, and associated melt, in scanning across the structure.

Abstract: The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and has situated upon the dielectric region a layer of recrystallized silicon as a second active region. A gate electrode overlies both active regions and serves as a mask to form in such respective regions self-aligned channels. The concentric placement of the active substrate monocrystalline silicon region, and inner perimeter of dielectric, and a further inner active region of recrystallized silicon situated over a dielectric region, facilitates recrystallization from seed of monocrystalline silicon irrespective of the direction of translation taken by the energy beam, and associated melt, in scanning across the structure.

Abstract: A process for selectively forming NMOS/PMOS/CMOS integrated circuits and for selectively incorporating any or all of lightly doped drain-source (LDD) regions, sidewall gate oxide structures, and guard band regions.

Abstract: A CMOS process incorporates self-aligned buried contacts, lightly doped source/drain structures, and sidewall oxide spacers. The process is tailored so that individual process steps and structural features serve several functions, thereby providing the desirable structural features and small geometry in conjunction with fast operational speeds, reduced Miller capacitance and short channel effects in a process of minimum complexity.

Abstract: A simplified small geometry MOS process incorporates a tungsten shunt layer on the thin silicon gate electrode layer allowing reduction of the thickness of the silicon layer and the use of an implant through the layer to form precisely controlled shallow source/drain regions without channeling. Lightly doped extension of the source and drain regions are automatically formed by an LDD implant following an isotropic undercutting etch of the silicon. The process is readily adapted to optional guard band implants and other beneficial structures such as gate sidewall oxide spacers.

Abstract: A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode. A relatively thick lift-off region is formed over and in alignment with the gate electrode. A thick oxide layer is then deposited over the structure so as to form stressed oxide extending from the lift-off layer sidewalls. A selective etch of the stressed oxide follows. The relatively thick oxide covering the lift-off layer is then removed with the etch of the lift-off layer, the lift-off etch acting through the exposed lift-off layer sidewalls. The formation of an upper field effect transistor gate oxide and a conformal deposition of polysilicon for the channel and source/drain regions follows. The conformally deposited polysilicon retains the contour of the recess formed by the lift-off.

Abstract: A process for fabricating aligned, stacked CMOS devices. Following the formation of the lower FET device, conformal undoped and doped oxide layers are formed thereover so that the level of the upper surface of the common gate electrode is above the doped oxide as formed in the source and drain regions of the lower FET device. A planarizing photoresist is then deposited and etched in conjunction with the oxide to the upper surface of the gate electrode. The exposed gate electrode is covered with a gate oxide layer, and a polycrystalline silicon layer for recrystallization to an upper FET device. Updiffusion from the residuals of doped oxide then creates an upper FET device with source and drain regions aligned to the gate oxide thereof and the underlying common gate electrode.

Abstract: A process for using selectively deposited tungsten in the making of ohmic contacts and contact/interconnect metallization patterns. In one form the process is employed to interconnect fully formed field effect devices using contacts through the dielectric layer. A thin layer of intrinsic polysilicon or amorphous silicon is conformally deposited, patterned and covered by selectively deposited tungsten, An anneal operation then forms self-aligned contacts or shunts, between the tungsten layer and the source/drain type diffusions exposed during the contact cut, by updiffusion through the thin intrinsic silicon, or by conversion of the thin intrinsic silicon to tungsten.

Abstract: An electrically programmable memory cell using selectively deposited tungsten on a sidewall to define a fuse region. Fabrication of the fuse structure involves only a single mask departure from standard MOSFET processing during which a selective isotropic etch of a silicon nitride sidewall structure facilitates the formation of a fuse structure comprised of a tungsten layer selectively deposited on exposed silicon and a source/drain diffusion separated by an oxide or selectively thinned oxide as the degenerating element. The actuation region of the fuse is proportional to the thickness of the selectively deposited tungsten layer.