Patents by Inventor Nicholas J. Wilt

Nicholas J. Wilt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7933202
    Abstract: Systems and methods for bounded minimal latency for network resources without synchronization are provided. In one embodiment, a method for managing data traffic between nodes in an asynchronous network comprises: receiving a data request message at a first port of network switch; storing information about the data request message in a memory at the network switch; forwarding the data request message to a producer node; receiving a data message at a second port of the network switch; determining whether the data message is responsive to the data request message; when the data message is responsive, forwarding the data message from the network switch; and when the data message is not responsive, blocking the data message from being forwarded from the network.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: April 26, 2011
    Assignee: Honeywell International Inc.
    Inventors: Scott Gray, Nicholas J Wilt
  • Patent number: 7929431
    Abstract: A communication network is provided. The network includes a least one switch and a plurality of ports. Each port is in communication with the at least one switch. At least one of the ports is configured to introduce a time delay after each transmission of a frame based at least in part on a maximum transmission rate of the at least one port and its allocated transmission rate.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: April 19, 2011
    Assignee: Honeywell International Inc.
    Inventors: Nicholas J Wilt, Scott Gray
  • Publication number: 20100195491
    Abstract: Systems and methods for bounded minimal latency for network resources without synchronization are provided. In one embodiment, a method for managing data traffic between nodes in an asynchronous network comprises: receiving a data request message at a first port of network switch; storing information about the data request message in a memory at the network switch; forwarding the data request message to a producer node; receiving a data message at a second port of the network switch; determining whether the data message is responsive to the data request message; when the data message is responsive, forwarding the data message from the network switch; and when the data message is not responsive, blocking the data message from being forwarded from the network.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 5, 2010
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Scott Gray, Nicholas J. Wilt
  • Patent number: 7512500
    Abstract: A method for initializing a chain of non-initialized data collectors is disclosed. The chain of non-initialized data collectors are coupled to a controller. In a first step communication between the controller and each data collector in the chain of non-initialized collectors is disabled, except for an active non-initialized data collector, The active non-initialized collector is coupled to the controller and any remaining non-initialized data collectors. Next, the active non-initialized data collector is initialized by assigning an identification number to the active non-initialized data collectors. The active non-initialized collector becomes an initialized data collector. Then, communication is restored between the initialized data collector and a next active non-initialized data collector in the chain of non-initialized data collectors. The method repeats until all non-initialized data collectors are initialized.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 31, 2009
    Assignee: Honeywell International, Inc.
    Inventors: Nicholas J. Wilt, Steven R. Thompson, Scott Gray
  • Publication number: 20080232253
    Abstract: A communication network is provided. The network includes a least one switch and a plurality of ports. Each port is in communication with the at least one switch. At least one of the ports is configured to introduce a time delay after each transmission of a frame based at least in part on a maximum transmission rate of the at least one port and its allocated transmission rate.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Nicholas J. Wilt, Scott Gray
  • Patent number: 7366627
    Abstract: A method is disclosed wherein a plurality of sensors mounted on a structure, a baseline data set for each of the plurality of sensors and a calibration procedure verify the integrity of a structural health management system. Initially a baseline data set is established. Before performing the structural health assessment a calibration-in data set for each of the plurality of sensors is collected. The calibration-in data set is compared to the baseline data set for each sensor of the plurality of sensors. If the calibration-in data set and the baseline data set match then a structure characterization is performed. If the calibration-in data set and the baseline data set do not match, a calibration-out procedure is performed to generate a calibration-out data set. If the calibration-out data set and the calibration-in data sets match, then a determination is made that the structural health management system was working.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: April 29, 2008
    Assignee: Honeywell International, Inc.
    Inventors: Grant A. Gordon, Nicholas J. Wilt, Joseph J. Nutaro
  • Patent number: 7263446
    Abstract: A structural health management system is disclosed. The structural health management system comprises a zone of sensors. A first sensor data collector is coupled to a first subset of the sensors in the zone; and a second sensor data collector coupled to a second subset of the sensors in the zone. In the present invention, loss of a sensor data collector does not result in the loss of ability to perform nondestructive testing in an entire zone.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: August 28, 2007
    Assignee: Honeywell International, Inc.
    Inventors: Brent A. Morin, Joseph J. Nutaro, Nicholas J. Wilt, Steven R. Thompson
  • Patent number: 6948091
    Abstract: Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane's memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: September 20, 2005
    Assignee: Honeywell International Inc.
    Inventors: Michael W. Bartels, Nicholas J. Wilt, Scott L. Gray
  • Publication number: 20030208704
    Abstract: Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane's memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Inventors: Michael W. Bartels, Nicholas J. Wilt, Scott L. Gray
  • Patent number: 5003195
    Abstract: A capacitor is charged and discharged through switch selectable resistors from regulated DC voltage supplies and clamping diodes to provide the bias signal to control the rise and fall times of the RF output pulse of a PIN diode attenuator. An isolation buffer isolates charging and discharging transients from the bias signal. An adjustable AC gain and adjustable DC offset inverting amplifier provides the isolation buffered signal to a high impedance, very low output AC impedance source for driving the bias input of the PIN diode attenuator. The DC offset is provided by an adjustable regulated voltage source coupled to the inverting amplifier.
    Type: Grant
    Filed: March 10, 1989
    Date of Patent: March 26, 1991
    Assignee: Honeywell Inc.
    Inventors: Desi Stelling, Robert J. Aleksa, Nicholas J. Wilt
  • Patent number: 4780792
    Abstract: An electronic component module is mounted on a motherboard. An elongated slot is formed in the module. A pair of ejector handles are mounted with the slot. A first leg portion of each handle is mounted on one side of the slot and a second leg portion is mounted on an opposite side of the slot. Each handle has a first end including an aperture formed in each leg and a second end including a flange. A pin connection extends through the apertures and the slot for pivotally and slidably connecting the handle to the module. Each handle is slidably movable from a first end of the slot to a second end of the slot adjacent a supporting chassis. The handles can then be pivoted outwardly away from the module until contacting the chassis, and then urged downwardly into engagement with the chassis thus unseating and lifting the module from nested engagement with the motherboard.
    Type: Grant
    Filed: October 5, 1987
    Date of Patent: October 25, 1988
    Assignee: Honeywell Inc.
    Inventors: Allan E. Harris, Norman M. Atkin, Nicholas J. Wilt
  • Patent number: 4683532
    Abstract: Verification of proper operation of computer programs executing in a central processor and protection of critical data is accomplished by an independent software monitor which accepts data keys from the executing program and outputs defined legitimate codes in response thereto. Legitimate codes and selected portions of input data keys are compared to validate proper softward execution.
    Type: Grant
    Filed: December 3, 1984
    Date of Patent: July 28, 1987
    Assignee: Honeywell Inc.
    Inventors: Larry J. Yount, Nicholas J. Wilt, Bryan H. Hill, Donald A. Peterson, Jr.